EM78P468NBQSSLASHNBQJ datasheet(12/82 Pages) EMC

12 / 82 page

EM78P468N/L

8-Bit Microcontroller

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Product Specification (V1.6) 12.31.2007

(This specification is subject to change without further notice)

6 Function Description

6.1 Operational Registers

6.1.1 R0/IAR (Indirect Addressing Register)

(Address: 00h)

R0 is not a physically implemented register. Its major function is to perform as an

indirect address pointer. Any instruction using R0 as a register, actually accesses the

data pointed by the RAM Select Register (R4).

6.1.2 R1/TCC (Timer Clock Counter)

(Address: 01h)

The Timer Clock Counter is incremented by an external signal edge applied to TCC, or

by the instruction cycle clock. It is written and read by the program as any other

6.1.3 R2/PC (Program Counter)

(Address: 02h)

The structure of R2 is depicted in Fig. 6-1, Program Counter Organization.

The configuration structure generates 4K

×13 bits on-chip ROM addresses to the

relative programming instruction codes.

The contents of R2 are all set to "0"s when a Reset condition occurs.

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows the PC to jump to any location within a page.

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto

the stack. Thus, the subroutine entry address can be located anywhere within a

page.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents

at the top of the stack.

"ADD R2, A" allows a relative address to be added to the current PC, and the ninth

and above bits of the PC will increase progressively.

"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of

the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.

The most significant bits (A10~A11) will be loaded with the content of PS0~PS1 in

the Status register (R3) upon execution of a "JMP" or "CALL" instruction.

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