EM78P468NBQSSLASHNBQJ datasheet(21/82 Pages) EMC

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EM78P468N/L

8-Bit Microcontroller

Product Specification (V1.6) 12.31.2007

• 15

(This specification is subject to change without further notice)

6.2 Special Purpose Registers

6.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the

temporary storage function of the Accumulator, which is not an addressable register.

Registers of IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = “0”)

6.2.2 IOC50/P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment

Control Register)

(Address: 05h, Bit 0 of R5 = “0”)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IOC57

IOC56

IOC55

IOC54

P8HS

P8LS

P7HS

P7LS

Bits 7~4 (IOC57~54):

Port 5 I/O direction control register

IOC5x = “0”:

set the relative P5.x I/O pins as output

IOC5x = “1”:

set the relative P5.x I/O pin into high impedance (input pin)

Bit 3 (P8HS):

Switch to high nibble I/O of Port 8 or to LCD segment output while

sharing pins with SEGxx/P8.x pins.

P8HS = “0”:

select high nibble of Port 8 as normal P8.4~P8.7

P8HS = “1”:

select LCD segment output as SEG 28~SEG 31 output

Bit 2 (P8LS):

Switch to low nibble I/O of Port 8 or to LCD segment output while sharing

pins with SEGxx/P8.x pins

P8LS = “0”:

select low nibble of Port 8 as normal P8.0~P8.3

P8LS = “1”:

select LCD Segment output as SEG 24~SEG 27 output

Bit 1 (P7HS):

Switch to high nibble I/O of Port 7 or to LCD segment output while

sharing pins with SEGxx/P7.x pins

P7HS = “0”:

select high nibble of Port 7 as normal P7.4~P7.7

P7HS = “1”:

select LCD Segment output as SEG 20~SEG 23 output

Bit 0 (P7LS):

Switch to low nibble I/O of Port 7 or to LCD segment output while sharing

pins with SEGxx/P7.x pins

P7LS = “0”:

select low nibble of Port 7 as normal P7.0~P7.3

P7LS = “1”:

select LCD segment output as SEG 16~SEG 19 output

EM78P468NBQS/NBQJ 数据表(PDF) 21 Page - ELAN Microelectronics Corp

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