ST63142 datasheet(31/86 Pages) STMICROELECTRONICS

31 / 86 page

The ST631xx devices offer two on-chip Timer pe-

ripherals consisting of an 8-bit counter with a 7-bit

programmable prescaler, thus giving a maximum

count of 2

15, and a control logic that allows config-

uring the peripheral operating mode. Figure 30

shows the timer block diagram. The content of the

8-bit

counters

can

read/written

the

Timer/Counter registers TCR that can be ad-

dressed in the data space as RAM location at ad-

dresses D3h (Timer 1) and DBh (Timer 2). The

state of the 7-bit prescaler can be read in the PSC

(Timer 2). The control logic is managed by TSCR

registers at D4h (Timer 1) and DCh (Timer 2) ad-

dresses as described in the following paragraphs.

The following description applies to both Timer 1

and Timer 2. The 8-bit counter is decrement by the

output (rising edge) coming from the 7-bit pres-

caler and can be loaded and read under program

control. When it decrements to zero then the TMZ

(timer zero) bit in the TSCR is set to one. If the ETI

(enable timer interrupt) bit in the TSCR is also set

to one an interrupt request, associated to interrupt

vector #3 (for Timer 1) and #1 for Timer 2, is gener-

ated. The interrupt of the timer can be used to exit

the MCU from the WAIT mode.

Figure 28. Timer Peripheral Block Diagram

TIMERS

The prescaler decrements on rising edge. The

prescaler input is the oscillator frequency divided

by 12 or an external clock at TIMER pin (this is not

available in ST631xx).

Depending on the division factor programmed by

PS2/PS1/PS0 (see table 9) bits in the TSCR, the

clock input of the timer/counter register is multi-

plexed to different sources.

On division factor 1, the clock input of the prescaler is

also that of timer/counter; on factor 2, bit 0 of prescaler

This bit changes its state with the half frequency of

prescaler clock input. On factor 4, bit 1 of PSC is

connected to clock input of TCR, and so on. On di-

vision factor 128, the MSB bit 6 of PSC is con-

nected to clock input of TCR. The prescaler

initialize bit (PSI) in the TSCR register must be set

to one to allow the prescaler (and hence the

counter) to start. If it is cleared to zero then all of

the prescaler bits are set to one and the counter is

inhibited from counting.

The prescaler can be given any value between 0

and 7Fh by writing to the related register address,

if bit PSI in the TSCR register is set to one. The tap

the

prescaler

selected

using

the

PS2/PS1/PS0 bits in the control register. Figure 33

shows the timer working principle.

ST63140,142,126,156

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