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ST63142 数据表(PDF) 46 Page - STMicroelectronics |
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ST63142 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 86 page ![]() 6-BIT PWM D/A CONVERTERS AND 62.5 kHz OUTPUT FUNCTION (Continued) DA0-DA5. These are the 6 bits of the PWM digital to analog converter. Undefined after reset. DAE. This is the D/A 1 enable bit. If zero, the out- put of the D/A is forced to zero; if one, the output of the D/A depends on bits DA0..DA5. Undefined af- ter reset. OUT1. This is the OUT1 data bit. The content of this bit is output on the OUT1 pin when the 62.5kHz frequency function is disabled (FO1 bit in DA0 reg- ister is cleared to zero). Undefined after reset. DA0-DA5. These are the 6 bits of the PWM digital to analog converter bits. Undefined after reset. DAE. This is the D/A 2 enable bit. If zero, the out- put of the D/A is forced to zero; if one, the output of the D/A depends on bits DA0..DA5. Undefined af- ter reset. IEN. This is the external interrupt enable. If set to one, the interrupt coming from the external inter- rupt pin is enabled, if this bit is cleared the interrupt is disabled. Undefined after reset. This interrupt is associated to the NMI interrupt vector. Refer to IR and interrupt descriptions for additional informa- tion. DA1 DA1 Data/Control Registers (E1h, Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 DAE D/A Enable Bit OUT1 Data Bit Figure 50. DA1 Data/Enable Register DA0-DA5. These are the 6 bits of the PWM digital to analog converter. Undefined after reset. DAE. This is the D/A 3 enable bit. If zero, the out- put of the D/A is forced to zero; if one, the output of the D/A depends on bits DA0..DA5. Undefined af- ter reset. ADSH. This is the analog to digital converter refer- ence voltage shift bit. If set to one, the AFC block has reference voltages on 1V border. If set to zero, on 0.5V border. Undefined after reset. Refer to AFC for additional information. DA2 DA2 Data/Control Registers (E2h Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 DAE D/A Enable Bit IEN IR Interrupt Enable Figure 51. DA2 Data/Enable Register DA3 DA3 Data/Contr ol Registers (E3h, Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 DAE D/A Enable Bit ADSH A/D ReferenceShift Figure 52. DA3 Data/Enable Register ® ST63140,142,126,156 42/82 |
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