ST63142 datasheet(52/86 Pages) STMICROELECTRONICS

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Table 15. OSD Control Registers and Data

RAM Addressing

Page

Address

00h - 3Fh

RAM Locations 00h - 3Fh

00h - 0Fh

RAM Locations 00h - 0Fh

10h

Vertical Start Register

11h

Horizontal Start Register

12h

Vertical Space Register

13h

Horizontal Space Register

14h

Background Control Register

17h

Global Enable Register

Page

EDh

Character Bank Select Register

OSD Global Enable Register

This register contains the global enable bit (GE). It

is the only register that can be written at any time

regardless of the state of the GE bit. It is a write

only register.

Global Enable

17h - Page 6

( Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

GE = Global Enable Bit

Unused

Figure 61. Global Enable Bit

ON-SCREEN DISPLAY (Continued)

D7-D1. These bits are not used

GE. Global Enable. This bit allows the entire dis-

play to be turned off.

“0” - The entire display is disabled. The RAM and

other registers of the OSD can be accessed by

the Core.

“1” - Display of words is controlled by the word en-

able bits (WE) located in the format or space char-

acter. The other registers and RAM cannot be

accessed by the Core.

VSAR

Vertical Start Address Register

(10h - Page 6, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

VSA5-VSA0 = Vertical Start

Address bits

FR = Fringe Backround

Control bit

Unuse d

Figure 62. Vertical Start Address Register

D7. This bit is not used

FR. Fringe Background.This bit changes the back-

ground from a box background to a fringe back-

ground. The background is enabled by word as

defined by either BG0 or BG1.

“0” - The background is defined to be a box which

is 7 x 9 dots.

“1” - T

The background is defined to be a fringe.

VSA5-VSA0. Vertical Start Address. These bits

determine the start position of the first line in the

vertical direction. The 6 bits can specify 63 display

start positions of interval 4h. The first start position

will be the fourth line of the display. The vertical

start address is defined VSA0 by the following for-

mula.

Vertical Start Address = 4h(2

5(VSA5) + 24(VSA4) +

3(VSA3) + 22(VSA2) + 21(VSA1) + 20(VSA0))

The case of all Vertical Start Address bits being

zero is illegal.

ST63140,142,126,156

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