ST63142 datasheet(53/86 Pages) STMICROELECTRONICS

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D7. This bit is not used.

SBD. Space Blanking Disable. This bit controls

whether or not the background is displayed when

outputting spaces. If two background colours are

used on adjacent words, then the background

should not be displayed on spaces in order to

make a nice break between colours. If an even

background around an area of text is desired, as in

a menu, then the background should be displayed

when outputting spaces.

“0” -The background during spaces is controlled by

the background enable bits (BG0 and BG1) lo-

cated in the Background Control register.

“1” -The background is not displayed when output-

ting spaces.

HSA5, HSA0 - Horizontal Start Address bits.

These bits determine the start position of the first

character in the horizontal direction. The 6 bits can

specify 64 display start positions of interval 2/fosc or

400ns. The first start position will be at 4.0

µs be-

cause of the time needed to access RAM and

ROM before the first character can be displayed.

The horizontal start address is defined by the fol-

lowing formula.

Horizontal Start Address = 2/fosc(10.0 + 2

5(HSA5)

4(HSA4) + 23(HSA3) + 22(HSA2) + 21(HSA1) +

0(HSA0))

D7. This bit is not used

SCB. Screen Blanking. This bit allows the entire

screen to be blanked.

“0” -The blanking output signal (VBLK) is active

only when displaying characters.

“1” -The blanking output signal (VBLK) is always

active. Characters in the display RAM are still

displayed.

When this bit is set to one, the screen is blanked

also without setting the Global Enable bit to one

(OSD disabled).

VS5 , VS0. Vertical Space. These bits determine

the spacing between lines if the Vertical Space En-

able bit (VSE) in the format character is one. If VSE

is zero there will be no spaces between lines. The

Vertical Space bits can specify one of 63 spacing

values from 4h to 252h. The space between lines

is defined by the following formula.

Space between lines = 4h(2

5(VS5) + 24(VS4) +

3(VS3) + 22(VS2) + 21(VS1) + 20(VS0))

The case of all Vertical Start Address bits being

zero is illegal.

HSAR

Horizontal Start Address Register

(11h - Page 6, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

HSA5-HSA0 = Horizontal Start

Address bits

SBD = Space Blanking

Disabled bit

Unused

Figure 63. Horizontal Start Address Register

ON-SCREEN DISPLAY (Continued)

VSR

Vertical Space Register

(12h - Page 6, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

VS5-VS0 = Vertical Space

SCB = Screen Blanking bit

Unuse d

Figure 64. Vertical Space Register

ST63140,142,126,156

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