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ST72141K2 数据表(PDF) 19 Page - STMicroelectronics |
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ST72141K2 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 132 page ![]() ST72141K 19/132 3.2 RESET MANAGER The RESET block includes three RESET sources as shown in Figure 11: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. A 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. Reset Block Diagram fCPU RESET RON VDD WATCHDOG RESET LVD RESET INTERNAL RESET |
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