ST72141K2 datasheet(39/132 Pages) STMICROELECTRONICS

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ST72141K

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MISCELLANEOUS REGISTER (Cont’d)

7.4 Miscellaneous Register Description

MISCELLANEOUS REGISTER (MISCR)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7 = XT16

MTC and SPI clock selection

This bit is set and cleared by software. The maxi-

mum allowed frequency is 4MHz.

0: MTC and SPI clock supplied with fOSC/2

1: MTC and SPI clock supplied with fOSC/4

Bit 6 = SSM

SS mode selection

This bit is set and cleared by software.

0: Normal mode - the level of the SPI SS signal is

the external SS pin.

1: I/O mode, the level of the SPI SS signal is read

from the SSI bit.

Bit 5 = SSI

SS internal mode

This bit replaces the SS pin of the SPI when the

SSM bit is set to 1. (see SPI description). It is set

and cleared by software.

Bits 4:3 = IS1[1:0]

EI1 sensitivity

The interrupt sensitivity defined using the IS1[1:0]

bits combination is applied to the EI1 external in-

terrupts. These two bits can be written only when

the I bit of the CC register is set to 1 (interrupt

masked).

EI1: Port B

Bits 2:1 = IS0[1:0]

EI0 sensitivity

The interrupt sensitivity defined using the IS0[1:0]

bits combination is applied to the EI1 external in-

terrupts. These two bits can be written only when

the I bit of the CC register is set to 1 (interrupt

masked).

EI0: Port A

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC / 2

1: Slow mode. fCPU = fOSC / 32

See sections on low power consumption mode

and MCC for more details.

Table 9. Miscellaneous Register Map and Reset Values

XT16 SSM

SSI

IS11

IS10

IS01

IS00

SMS

IS11 IS10

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

IS01 IS00

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

Address

(Hex.)

Label

7654

3210

0020h

MISCR

Reset Value

XT16

SSM

SSI

IS11

IS10

IS01

IS00

SMS

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