ST72141K2 datasheet(60/132 Pages) STMICROELECTRONICS

60 / 132 page

ST72141K

60/132

MOTOR CONTROLLER (Cont’d)

8.1.4.3 PWM Manager

The PWM manager controls the motor via the six

output channels in voltage mode or current mode

depending on the V0C1 bit in the MCRA register.

A block diagram of this part is given in Figure 37.

Voltage Mode

In Voltage mode (V0C1 bit = ”0”), the PWM is gen-

erated by the 16-bit A Timer.

Its duty cycle is programmed by software (refer to

the chapter on the 16-bit Timer) as required by the

application (speed regulation for example).

The current comparator is used for safety purpos-

es as a current limitation. For this feature, the de-

tected current must be present on the MCCFI pin

and the current limitation must be present on pin

OCP1A. This current limitation is fixed by a voltage

reference depending on the maximum current ac-

ceptable for the motor. This current limitation is

generated with the VDD voltage by means of an

external divider but can also be adjusted with an

external reference voltage (

≤ 3.7 V). The external

components are adjusted by the user depending

on the application needs. In Voltage mode, it is

mandatory to set a current limitation.

In sensorless mode the BEMF zero crossing is

done during the PWM off time.

The PWM signal is directed to the channel manag-

er that connects it to the programmed outputs

(See Figure 39).

Current Mode

In current mode, the PWM output signal is gener-

ated by a combination of the output of the meas-

urement window generator (see Figure 38) and

the output of the current comparator, and is direct-

ed to the output channel manager as well (Figure

39).

The current reference is provided to the compara-

tor by the PWM output of the 16-bit Timer (0.25%

accuracy), filtered through a RC filter (external ca-

pacitor on pin OCP1A and an internal voltage di-

vider 30K and 70K).

The detected current input must be present on the

MCCFI pin.

To avoid spurious commutations due to parasitic

noise after switching on the PWM, a 2.5-µs filter

can be applied on the comparator output by set-

ting the CFF bit in the MCRB register.

The On state of the resulting PWM starts at the

end of the measurement window (rising edge),

and ends either at the beginning of the next meas-

urement window (falling edge), or when the cur-

rent level is reached.

Figure 37. Current Feedback

MCCFI

2.5-

µs Filter

VCREF

16-bit Timer - PWM

OCP1A

CEXT

Common Mode = VDD - (1,4...1,0)V

VCREF MAX = VDD - 1,3 V

Power down mode

To Phase State

V0C1 bit

CFF bit

Sampling frequency

Control

MCRA Register

MCRA

(V)

R1ext

R2ext

VDD

(V)

(I)

LEGEND:

(I): Current mode

(V): Voltage mode

ST72141K2 数据表(PDF) 60 Page - STMicroelectronics

ST72141K2 数据表(HTML) 60 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载