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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5 RESET AND CLOCK CONTROL UNIT (RCCU)

5.1 INTRODUCTION

The Reset and Clock Control Unit (RCCU) com-

prises two distinct sections:

– the Clock Control Unit, which generates and

manages the internal clock signals.

– the Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog gener-

ated resets.

In Stop mode and Halt mode, all oscillators are fro-

zen in order to achieve the lowest possible power

consumption.

Entering and exiting Stop mode is controlled by

the WUIMU.

Halt mode is entered by executing the HALT in-

struction. Halt mode can only be exited by a reset

event.

5.2 CLOCK CONTROL UNIT

The Clock Control Unit generates the internal

clocks for the CPU core (CPUCLK) and for the on-

chip peripherals (INTCLK). The Clock Control Unit

may be driven by an external crystal circuit, con-

nected to the OSCIN and OSCOUT pins, or by an

external pulse generator, connected to OSCIN

(see Figure 34 and Figure 36). If present, another

clock source named CK_AF can be provided to

the system. Depending on the device, it can be a

periodic signal applied to the CK_AF pin or a sig-

nal generated internally by the MCU (RC oscilla-

tor).

5.2.1 Clock Control Unit Overview

As shown in Figure 26, a programmable divider

can divide the CLOCK1 input clock signal by two.

The resulting signal, CLOCK2, is the reference in-

put clock to the programmable Phase Locked

Loop frequency multiplier, which is capable of mul-

tiplying the clock frequency by a factor of 6, 8, 10

or 14; the multiplied clock is then divided by a pro-

grammable divider, by a factor of 1 to 7. By this

means, the ST9 can operate with cheaper, medi-

um frequency (3-5 MHz) crystals, while still provid-

ing a high frequency internal clock for maximum

system performance; the range of available multi-

plication and division factors allow a great number

of operating clock frequencies to be derived from a

single crystal frequency. The undivided PLL clock

is also available for special purposes (high-speed

peripheral).

For low power operation, especially in Wait for In-

terrupt mode, the Clock Multiplier unit may be

turned off, whereupon the output clock signal may

be programmed as CLOCK2 divided by 16. Fur-

thermore, during the execution of a WFI in Low

Power mode, the CK_AF clock is automatically di-

vided by 16 for further consumption reduction. (for

the selection of this signal refer to the description

the CK_AF clock source in the following sections

of this chapter).

The internal system clock, INTCLK, is routed to all

on-chip peripherals, as well as to the programma-

ble Clock Prescaler Unit which generates the clock

for the CPU core (CPUCLK).

The Clock Prescaler is programmable and can

slow the CPU clock by a factor of up to 8, allowing

the programmer to reduce CPU processing speed,

and thus power consumption, while maintaining a

high speed clock to the peripherals. This is partic-

ularly useful when little actual processing is being

done by the CPU and the peripherals are doing

most of the work.

Figure 26. Clock Control Unit Simplified Block Diagram

Quartz

CK_AF

1/16

1/2

oscillator

CLOCK2

CLOCK1

CK_AF

PLL

Clock Multiplier

CPU Clock

Prescaler

CPU Core

Peripherals

CPUCLK

INTCLK

Unit

/Divider

1/16

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