ST92141 datasheet(50/179 Pages) STMICROELECTRONICS

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ST92141 - INTERRUPTS

NMI/WKP0 LINE MANAGEMENT (Cont’d)

3.9.1 NMI/Wake-Up Event Handling in Run

mode

The four external lines WKUP0/NMI, WKUP1-3

can also be used when the device is in Run Mode.

In addition, if the WKUP0/NMI line is used and the

NMI and WKUP0 events are enabled by program-

ming the CPU, IMC and WUIMU registers, a tran-

sition on the input pin can generate the following

events:

– IMC: the six output phases UH/UL/VH/VL/WH/

WL are released in High Impedance. The NMI bit

of the IMCIVR register is automatically set to “1”.

A non maskable interrupt request is then sent to

the CPU.

– CPU: the NMI pending bit of the CICR register is

set and the corresponding NMI interrupt routine

is immediately executed.

Note 1: The NMI pending bits of the IMCIVR reg-

ister must be cleared by software in the NMI rou-

tine, whereas the NMI pending bit of the CICR

is acknowledged.

Note 2: The external NMI/WKUP0 event is flagged

in the NMI pending bit of the IMCIVR register. The

NMI routine must clear this bit. This operation must

occur after disactivation of the NMI/WKUP0 line

(otherwise, the next NMI/WKUP0 event will be

lost, if the CPU is sensitive to a rising edge on the

NMI input).

The flexibility of the ST9 also allows the use of the

NMI/WKUP0 line as a wake up function only or as

a Non Maskable Interrupt only.

WARNING:

1. The NMI management implemented in the

ST92141 imposes the following constraints on

the P5.3 (NMI/WKUP0) I.O pin:

– No glitches should occur on the pin to avoid un-

intentional NMI/wake up requests.

– A minimum pulse width is requested for the pin

activation (refer to ST92141 Electrical Specifica-

tion).

2. The WKUP0-3 management implemented in

the ST92141 imposes the following constraints

on the P5.0 (WKUP1), P5.2 (WKUP0), P3.2

(WKUP3) and P3.6 (WKUP2):

– No glitches should occur on WKUP0-3 pins to

avoid unintentional requests.

3.9.2 NMI/Wake-Up Event Handling in STOP

mode

The ST92141 enters Stop Mode by software writ-

ing a special Stop bit setting sequence in the

WUCTRL register of the WUIMU. After entering

Stop Mode, the device can be woken up by one of

the four Wake Up external lines (refer to Section

3.12 WAKE-UP / INTERRUPT LINES MANAGE-

MENT UNIT (WUIMU).

In addition, if the WKUP0/NMI line is used and the

NMI and WKUP0 events are enabled by program-

ming the CPU, IMC and WUIMU registers, a tran-

sition on the input pin can generate the following

events:

– IMC: the six output phases UH/UL/VH/VL/WH/

WL are released in High Impedance. The NMI bit

of the IMCIVR register is automatically set to “1”.

A non maskable interrupt request is then sent to

the CPU.

– WUIMU: the NMI/WKUP0 activation wakes up

the ST92141 from Stop mode, allowing the CPU

to acknowledge the NMI request from IMC

– CPU: the NMI pending bit of the CICR register is

set and the corresponding NMI interrupt routine

is executed as soon as the ST92141 is exited

from Stop mode.

Note: The NMI pending bits of the IMCIVR register

must be cleared by software in the NMI routine,

whereas the NMI pending bit of the CICR register

is cleared by hardware when the NMI routine is ac-

knowledged.

3.9.3 Unused Wake Up Management Unit lines

The WUIMU can manage up to 16 External-Inter-

rupt/ Wake up lines. Usually, only a subset of

these 16 lines is used.

In the ST92141, 4 lines out of 16 are available as

external lines (WKUP0/1/2/3) but the Pending and

Mask bits of the unused lines (WKUP4 to WKUP

15) are also accessible by software (refer to Sec-

tion 3.12 WAKE-UP / INTERRUPT LINES MAN-

AGEMENT UNIT (WUIMU)). Therefore, it is possi-

ble to generate a software interrupt by disabling

the Mask and by setting the Pending bit of an un-

used channel.

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