ST92141 datasheet(69/179 Pages) STMICROELECTRONICS

69 / 179 page

69/179

ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.4 CLOCK CONTROL REGISTERS

MODE REGISTER (MODER)

R235 - Read/Write

System Register

Reset Value: 1110 0000 (E0h)

*Note:

This register contains bits which relate to

other functions; these are described in the chapter

dealing with Device Architecture. Only those bits

relating to Clock functions are described here.

Bit 5 = DIV2:

OSCIN Divided by 2.

This bit controls the divide by 2 circuit which oper-

ates on the OSCIN Clock.

0: No division of the OSCIN Clock

1: OSCIN clock is internally divided by 2

Bit 4:2 = PRS[2:0]:

Clock Prescaling.

These bits define the prescaler value used to pres-

cale CPUCLK from INTCLK. When these three

bits are reset, the CPUCLK is not prescaled, and is

equal to INTCLK; in all other cases, the internal

clock is prescaled by the value of these three bits

plus one.

CLOCK CONTROL REGISTER (CLKCTL)

R240 - Read Write

Reset Value: 0000 0000 (00h)

Bit 7 = INT_SEL:

Interrupt Selection.

0: Select the external interrupt pin as interrupt

source (Reset state)

1: Select the internal RCCU interrupt (see Section

5.3.5)

Bit 4:6 = Reserved.

Must be kept reset for normal operation.

Bit 3 = SRESEN:

Software Reset Enable.

0: The HALT instruction turns off the quartz, the

PLL and the CCU

1: A Reset is generated when HALT is executed

Bit 2 = CKAF_SEL:

Alternate Function Clock Se-

lect.

0: CK_AF clock not selected

1: Select CK_AF clock

Note: To check if the selection has actually oc-

curred, check that CKAF_ST is set. If no clock is

present on the CK_AF pin, the selection will not

occur.

Bit 1 = WFI_CKSEL:

WFI Clock Select.

This bit selects the clock used during Low power

WFI mode if LPOWFI = 1.

0: INTCLK during WFI is CLOCK2/16

1: INTCLK during WFI is CK_AF, further divided

by 16, providing it is present. In effect this bit

sets CKAF_SEL in WFI mode

WARNING: When the CK_AF is selected as Low

Power WFI clock but the XTAL is not turned off

(R242.4 = 0), after exiting from the WFI, CK_AF

will be still selected as system clock. In this case,

reset the R240.2 bit to switch back to the XT.

Bit 0 = LPOWFI:

Low Power mode during Wait For

Interrupt.

0: Low Power mode during WFI disabled. When

WFI is executed, the CPUCLK is stopped and

INTCLK is unchanged

1: The ST9 enters Low Power mode when the WFI

instruction is executed. The clock during this

state depends on WFI_CKSEL

DIV2

PRS2

PRS1

PRS0

INT_SEL

SRESEN CKAF_SEL WFI_CKSEL LPOWFI

ST92141 数据表(PDF) 69 Page - STMicroelectronics

ST92141 数据表(HTML) 69 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载