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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

3.12.4.2 Simultaneous Setting of Pending Bits

It is possible that several simultaneous events set

different pending bits. In order to accept subse-

quent events on external wake-up/interrupt lines, it

is necessary to clear at least one pending bit: this

operation allows a rising edge to be generated on

the INTD1 line (if there is at least one more pend-

ing bit set and not masked) and so to set EIPR.7

bit again. A further interrupt on channel INTD1 will

be serviced depending on the status of bit EIMR.7.

Two possible situations may arise:

1. The user chooses to reset all pending bits: no

further interrupt requests will be generated on

channel INTD1. In this case the user has to:

– Reset EIMR.7 bit (to avoid generating a spuri-

ous interrupt request during the next reset op-

eration on the WUPRH register)

– Reset WUPRH register using a read-modify-

write instruction (AND, BRES, BAND)

– Clear the EIPR.7 bit

– Reset the WUPRL register using a read-mod-

ify-write instruction (AND, BRES, BAND)

2. The user chooses to keep at least one pending

bit active: at least one additional interrupt

request will be generated on the INTD1 chan-

nel. In this case the user has to reset the

desired pending bits with a read-modify-write

instruction (AND, BRES, BAND). This operation

will generate a rising edge on the INTD1 chan-

nel and the EIPR.7 bit will be set again. An

interrupt on the INTD1 channel will be serviced

depending on the status of EIMR.7 bit.

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