ST92141 datasheet(49/179 Pages) STMICROELECTRONICS

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ST92141 - INTERRUPTS

3.9 NMI/WKP0 LINE MANAGEMENT

In the ST92141, the Non Maskable Interrupt (NMI)

and the Wake Up 0 line (WKUP0) functionalities

are both physically mapped on the same I/O Port

pin P5.1 (refer to Section 1.2).

The NMI/WKUP0 is a single alternate function In-

put, associated with pin P5.1. It is input to the In-

duction Motor Controller (IMC) and the Wake Up

Management Unit (WUIMU).

The IMC Controller processes the NMI Input and

generates the Non Maskable Interrupt request to

the CPU (refer to Figure 24 and IMC Figure 71).

Figure 24. NMI/WKUP0 Line Management

NMI Event Handling

To enable an NMI event on the NMI/WKUP0 line,

the following bits must be programmed:

– TLNM bit in the NICR register,

– TLI and IEN bits in the CICR register

– NMI bit in the IMCIVR register

– NMIL bit in the PBR register

– NMIE bit in the PCR1 register

An event on the NMI/WKUP0 line is handled by

the ST92141 in the following way:

– a NMI event is acknowledged in the CPU only

when the internal clock INTCLK is running (i.e.

when the ST92141 is not in Stop Mode).

– a NMI event is immediately acknowledged in the

IMC. The ST92141 can be either in Stop or in

Run Mode (the NMI/WKUP0 line is detected

asynchronously).

Wake-up Event Handling

To enable a wake-up event on the NMI/WKUP0

line, the following bits must be programmed:

– WUMx bits in the WUMRL register

– WUTx bits in the WUTRL register

An event on the NMI/WKUP0 or the WKUP[3:1]

lines is handled by the ST92141 in the following

way:

– a wake up event of one external line (out of the

four available), is immediately acknowledged in

the WUIMU. The ST92141 can be either in Stop

or in Run mode (the NMI/WKUP0 and

WKUP[3:1] lines are detected asynchronously).

UH/UL/VH

VL/WH/WL

Input Buffer

CPU

WUIMU

Output Buffers

P5.1

IMC

Stop request to RCCU

NMI/WKUP0

WKUP0

NMI

NMI to CPU

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