ST92141 datasheet(153/179 Pages) STMICROELECTRONICS

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ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)

COMPARE RESULT REGISTER (CRR)

R252 - Read/Write

Reset Value: 0000 1111 (0Fh)

The result of the comparison between the current

value of data registers 6 and 7 and the threshold

registers is stored in the 4 most significant bits of

this register.

Bit 7 = C7U:

Compare Reg 7 Upper threshold

Set when converted data is greater than or equal

to the threshold value. Not affected otherwise.

Bit 6 = C6U:

Compare Reg 6 Upper threshold

Set when converted data is greater than or equal

to the threshold value. Not affected otherwise.

Bit 5 = C7L:

Compare Reg 7 Lower threshold

Set when converted data is less than the threshold

value. Not affected otherwise.

Bit 4 = C6L:

Compare Reg 6 Lower threshold

Set when converted data is less than the threshold

value. Not affected otherwise.

These bits should be reset at the end of the “Out of

Range” interrupt service routine.

Note: Any software reset request of the ICR, will

also cause all the compare status bits to forced by

hardware to zero, in order to prevent possible

overwriting if an interrupt request occurs between

reset and the Interrupt request software reset.

Bit 3 = undefined, return '1' when red.

Bit 2:0 = PR[2:0]:

Clock divider bits

These bits enable a frequency division factor de-

pending on the value stored:

Table 30. Frequency Division Factors

Warning: If the prescaler programming value is

changed during a conversion, the user has to re-

start the conversion (i.e. simply rewriting the CLR

C7U

C6U

C7L

C6L

PR2

PR1

PR0

PR[2:0]

bits

Freq. Div.

Factor

(FDF)

Max. con-

version

time

(INTCLK)

Min. sam-

pling time

(INTCLK)

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

138

552

828

1104

1380

1656

1932

2208

336

504

672

840

1008

1176

1344

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