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ADE7569 数据表(PDF) 105 Page - Analog Devices |
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ADE7569 数据表(HTML) 105 Page - Analog Devices |
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105 / 136 page  Preliminary Technical Data ADE7566/ADE7569 Rev. PrA | Page 105 of 136 PLL The ADE7566/ADE7569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power savings when maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy measurement clock is derived from the PLL clock and is maintained at 4.096 MHz/5 MHz, 819.2 kHz across all CD settings. The PLL is controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR (POWCON, 0xC5), a key is required to modify the register. First, the Key SFR (KYREG, 0xC1) is written with the key, 0xA7, and then a new value is written to the Power Control SFR (POWCON, 0xC5). If the PLL loses lock, the MCU is reset and the PLL_FLT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT bit. PLL SFR REGISTER LIST Table 111. Power Control SFR (POWCON, 0xC5) Bit No. Mnemonic Default Description 7 Reserved 0 Reserved. 6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0 5 Reserved 0 Reserved. 4 COREOFF 0 Set this bit to shut down the core if in the PSM1 operating mode. 3 Reserved Reserved. Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD CD[2:0] Result (fCORE in MHz) 000 4.096 001 2.048 010 1.024 011 0.512 100 0.256 101 0.128 110 0.064 2 to 0 CD[2:0] 010 111 0.032 Table 112. Key SFR (KYREG, 0xC1) Bit No. Mnemonic Default Description 7 to 0 KYREG 0 Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it. Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping registers to unlock it. Table 113. Peripheral Configuration SFR (PERIPH, 0xF4) Bit No. Mnemonic Default Description 7 RXFLAG 0 If set, indicates that a Rx edge event triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is connected internally to VSW. If set, VSW = VDD. If cleared, VSW = VBAT. 5 VDD_OK 0 If set, indicates that VDD power supply is ok for operation. 4 PLL_FLT 0 If set, indicates that PLL is not locked. 3 Reserved Reserved. 2 EXTREFEN 0 Set this bit if an external reference is connected to the REFIN pin. Controls the function of the P1.0/RxD pin. RXPROG [1:0] Result 00 GPIO 01 Rx with wake-up disabled 1 to 0 RXPROG[1:0] 00 11 Rx with wake-up enabled |
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