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ADE7569 数据表(PDF) 108 Page - Analog Devices |
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ADE7569 数据表(HTML) 108 Page - Analog Devices |
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108 / 136 page  ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 108 of 136 Table 116. RTC Configuration SFR (TIMECON, 0xA1) Bit No. Mnemonic Default Description 7 MIDNIGHT 0 Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is raised once a day at midnight. Twenty-Four Hour Mode. This bit is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). TFH Result 0 256-Hour Mode. The HOUR register rolls over from 255 to 0. 6 TFH 0 1 24-Hour Mode. The HOUR register rolls over from 23 to 0. Interval Timer Time-Base Selection. ITS[1:0] Result (Time base) 00 1/128 sec. 01 Second. 10 Minute. 5 to 4 ITS[1:0] 0 11 Hour. Interval Timer 1 Time Alarm. SIT Result 0 The ALARM flag is set after INTVAL counts and then another interval count starts. 3 SIT 0 1 The ALARM flag is set after one time interval. 2 ALARM 0 Interval Timer Alarm Flag. This bit is set when the configured time interval has elapsed. It can be cleared by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code. Interval Timer Enable. ITEN Result 0 The interval timer is disabled. The 8-bit interval timer counter is reset. 1 ITEN 0 1 Set this bit to enable the interval timer. The RTCEN bit must also be set to enable the interval timer. 0 RTCEN 1 RTC Enable. Also Temperature, Battery and Supply ADC Background Strobe Enable. Note that the RTC is always enabled. Table 117. Hundredths of a Second Counter SFR (HTHSEC, 0xA2) Bit No. Mnemonic Default Description 7 to 0 HTHSEC 0 This counter updates every 1/128 sec, referenced from the calibrated 32 kHz clock. It overflows from 127 to 00, incrementing the seconds counter (SEC). This register is retained during a watchdog reset or an external reset. It is reset after a POR. Table 118. Seconds Counter SFR (SEC, 0xA3) Bit No. Mnemonic Default Description 7 to 0 SEC 0 This counter updates every second, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00, incrementing the minutes counter (MIN). This register is retained during a watchdog reset or an external reset. It is reset after a POR. Table 119. Minutes Counter SFR (MIN, 0xA4) Bit No. Mnemonic Default Description 7 to 0 MIN 0 This counter updates every minute, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00, incrementing the hours counter, HOUR. This register is retained during a watchdog reset or an external reset. It is reset after a POR. Table 120. Hours Counter SFR (HOUR, 0xA5) Bit No. Mnemonic Default Description 7 to 0 HOUR 0 This counter updates every hour, referenced from the calibrated 32 kHz clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. If the TFH bit is cleared, the HOUR SFR overflows from 255 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. This register is retained during a watchdog reset or an external reset. It is reset after a POR. |
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