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ADE7569 数据表(PDF) 109 Page - Analog Devices |
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ADE7569 数据表(HTML) 109 Page - Analog Devices |
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109 / 136 page  Preliminary Technical Data ADE7566/ADE7569 Rev. PrA | Page 109 of 136 Table 121. Alarm Interval SFR (INTVAL, 0xA6) Bit No. Mnemonic Default Description 7 to 0 INTVAL 0 The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a pending RTC interrupt is created. Note that the interval counter is 8-bits. Therefore, it could count up to 255 sec, for example. Table 122. RTC Nominal Compensation SFR (RTCCOMP, 0xF6) Bit No. Mnemonic Default Description 7 to 0 RTCCOMP 0 The RTCCOMP SFR holds the nominal RTC compensation value at 25°C. This register is retained during a watchdog reset or an external reset. It is reset after a POR. Table 123. RTC Temperature Compensation SFR (TEMPCAL, 0xF7) Bit No. Mnemonic Default Description 7 to 0 TEMPCAL 0 The TEMPCAL SFR is adjusted based on the temperature read in the TEMPADC to calibrate the RTC over temperature. This allows the external crystal shift to be compensated over temperature. This register is retained during a watchdog reset or an external reset. It is reset after a POR. Table 124. Interrupt Pins Configuration SFR (INTPR, 0xFF) Bit No. Mnemonic Default Description 7 RTCCAL 0 Controls the RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window. FSEL[1:0] Result (Calibration window, frequency) 0 0 30.5 sec, 1 Hz 0 1 30.5 sec, 512 Hz 1 0 0.244 sec, 500 Hz 6 to 5 FSEL[1:0] 1 1 0.244 sec, 16.384 kHz 4 Reserved Controls the function of INT1. INT1PRG[2:0] Result x 0 0 GPIO x 0 1 BCTRL 0 1 x INT1 input disabled 3 to 1 INT1PRG[2:0] 000 1 1 x INT1 input enabled Controls the function of INT0. INT0PRG Result 0 INT0 input disabled 0 INT0PRG 0 1 INT0 input enabled Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF) To protect the RTC from runaway code, a key must be written to the KYREG register to obtain write access to the Interrupt Pins Configuration SFR (INTPR, 0xFF). The KYREG should be set to 0xEA to unlock this SFR and resets to zero after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code: MOV KYREG, #0EAh MOV INTPR, #080h Table 125. Key SFR (KYREG, 0xC1) Bit No. Mnemonic Default Description 7 to 0 KYREG 0 Write 0xA7 to the this SFR before writing to the POWCON SFR, which unlocks KYREG. Write 0xEA to the this SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping registers to unlock KYREG. |
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