ADE7569 datasheet(112/136 Pages) AD

112 / 136 page

ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 112 of 136

UART SERIAL INTERFACE

The ADE7566/ADE7569 UART can be configured in one of

four modes.

•

Shift register with baud rate fixed at fCORE/12

•

8-bit UART with variable baud rate

•

9-bit UART with baud rate fixed at fCORE/64 or fCORE/32

•

9-bit UART with variable baud rate

Variable baud rates are defined by using an internal timer to

generate any rate between 300 baud/sec and 115,200 baud/sec.

The UART serial interface provided in the ADE7566/ADE7569

is a full-duplex serial interface. It is also receive buffered by

storing the first received byte in a receive buffer until the

reception of the second byte is complete. The physical interface

to the UART is provided via the RxD (P1.0) and TxD (P1.1)

pins, while the firmware interface is through the SFRs presented

in Table 127.

Both the serial port receive and transmit registers are accessed

through the Serial Port Buffer SFR (SBUF, 0x99). Writing to

SBUF loads the transmit register, and reading SBUF accesses a

physically separate receive register.

An enhanced UART mode is offered by using the UART timer

and by providing enhanced frame error, break error, and

overwrite error detection. This mode is enabled by setting the

EXTEN bit in the Configuration SFR (CFG, 0xAF) (see the

UART Additional Features section). The Enhanced Serial Baud

Rate Control SFR (SBAUDT, 0x9E) and UART Timer Fractional

Divider SFR (SBAUDF, 0x9D) are used to configure UART

timer and to indicate the enhanced UART errors.

UART SFR REGISTERS

Table 127. Serial Port SFRs

SFR

Address

Bit Addressable

Description

SCON

0x98

Yes

Serial Communications Control Register (see Table 128).

SBUF

0x99

Serial Port Buffer (see Table 129).

SBAUDT

0x9E

Enhanced Error Checking (see Table 130).

SBAUDF

0x9D

Enhanced Fractional Divider (see Table 131).

Table 128. Serial Communications Control Register Bit Description SFR (SCON, 0x98)

Bit No.

Address

Mnemonic

Default

Description

UART Serial Mode Select Bits. These bits select the serial port operating mode.

SM[0:1]

Result (Selected Operating Mode)

Mode 0, shift register, fixed baud rate (fCORE/12).

Mode 1, 8-bit UART, variable baud rate.

Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16).

7 to 6

0x9F, 0x9E

SM0, SM1

Mode 3, 9-bit UART, variable baud rate.

0x9D

SM2

Multiprocessor Communication Enable Bit. Enables multiprocessor communication in

Mode 2 and Mode 3, and framing error detection in Mode 1.

In Mode 0, SM2 should be cleared.

In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received.

If SM2 is cleared, RI is set as soon as the byte of data is received.

In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.

If SM2 is cleared, RI is set as soon as the byte of data is received.

0x9C

REN

Serial Port Receive Enable Bit. Set by user software to enable serial port reception.

Cleared by user software to disable serial port reception.

0x9B

TB8

Serial Port Transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in

Mode 2 and Mode 3.

0x9A

RB8

Serial Port Receiver Bit 9. The ninth data bit received in Mode 2 and Mode 3 is latched

into RB8. For Mode 1, the stop bit is latched into RB8.

0x99

Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0 or

at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3.

TI must be cleared by user software.

0x98

Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or

halfway through the stop bit in Mode 1, Mode 2, and Mode 3.

RI must be cleared by user software.

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