STLC5046 datasheet(7/27 Pages) STMICROELECTRONICS

7 / 27 page

FUNCTIONAL DESCRIPTION

POWER ON INITIALIZATION

When power is first applied it is recommended to

reset

the

device by

forcing the

condition

M1.0=00, in order to to clear all the internal regis-

ters.

In MCU mode M0 is set steadily Low and the de-

vice is reset by applying a negative pulse to M1

(its operative level in MCU mode is High); same

result can be obtained by writing an High level

into the control bit RES of the CONF register.

In Pin-strap mode M1 is set steadily Low and the

device is reset by applying a negative pulse to

M0 (its operative level in Pin-strap mode is High);

at the end of the Reset phase (M0=High) the de-

vice is programmed according to the logical con-

figuration of the control pins.

During the Reset condition all the I/On and CS_n

pins are set as inputs , DX is set in high imped-

ance and all VFROn outputsare forced to AGND.

POWER DOWN STATE

Each of the four channel may be put into power

down mode by setting the appropriate bit in the

CONF register or strapping to VDD the proper

pin. In this mode the eventual programmed DX

channel is set in high impedance while the VFRO

outputs are forced to AGND. In Pin strap mode

the value forced on the input pin is internally up-

dated every FS signal.

TRANSMIT PATH

The analog VFXI signal through

an amplifier

stage is applied to a PCM converter and the cor-

responding digital signal is sent to DX output.

In MCU mode, the amplifier gain can be pro-

grammed with two different values by means of

TXG Reg. : 0dB or +3.52 dB.

A programmable gain block after the A/D conver-

sion allows to set transmit gain in 12dB range,

with steps <0.1dB by writing proper code into

GTXn register.

Setting GTXn=00h , the transmitted signal is

muted, i.e. an idle PCM signal is generated on

DX.

µ coding Law is selected by bit5 (AMU) of

CONF reg.

Setting LIN=1 (bit6 of CONF reg.) the Linear cod-

ing Law is selected (16bits); in this case the sig-

nal sent on DX will take two adjacent PCM time

slots.

In Pin-strap mode, the amplifier gain is set to

0dB; only two values of Transmit gain can be se-

lected according to the level of GXn control input

(in Pin-strap):

GXn=1

selects

the

gain

corresponding

GTXn=FFh (0dB)

GXn=0

selects

the

gain

corresponding

GTXn=8Fh ( -3.5dB)

Different gain value is obtained through proper

voltage divider.

µ coding Law is selected according to AMU pin

level:

AMU=0

µ-Law selected.

AMU=1

A-Law selected.

VFXI input must be AC coupled to the signal

source; the voltage swing allowed is 1.0Vpp

VFRO

A/µ

8 bit linear

1/4 to 1

Σ∆

conv.

RXG:

0dB

-1.94d B

-4.44d B

-7.96d B

-13. 98dB

for RXG=0dB; GR=0dB (FF)

0dBm0 => -3dBm|600Ω

Figure 2. Receive path.

VFXI

TXG: 0dB

+3.52dB

Ω

Σ∆

conv.

8 bit linear

1/4 to 1

AGND

for TXG=0dB; GX=0dB (FF)

-15dBm|600Ω

0dBm0

Figure 1. Transmit path.

STLC5046

7/27

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