STLC5046 datasheet(10/27 Pages) STMICROELECTRONICS

10 / 27 page

In pin-strap mode the status of the control pins is

entered at power-on reset and refreshed at any

Frame Sync. cycle.

In MCU mode the control information is written to

or read from STLC5046 via the serial four wires

control bus :

CCLK : Control Clock

: Chip Select input

: Serial Data input

: Serial Data output

All control instructions require 2 bytes, with the ex-

ception of the single byte for command synchroni-

zation. The first byte specify the register address,

and the type of access (Read or Write).

The second byte contain the data to be loaded into

the register (on CI wire) or carried out the register

content (on CO wire) depending on the R/W bit of

the first byte. CO wire is normally in High Imped-

ance and goes to low impedance only during the

second byte in case of Read operation. This allows

to use a common wire for both CI/CO.

Serial data CI is shifted to the serial input register

on the rising edge of CCLK and CO is shifted out

on the falling.

CS, normally High, is set Low during the trans-

mission / reception of a byte, lasting

8CCLK

pulses .

Though, in general, two bytes of the same in-

struction take

two

separated cycles

STLC5046 can handle the data transfer in a sin-

gle 16 CCLK CS cycle, in both the directions.

One additional wire provided to the control inter-

face is an open drain interrupt output (INT) that

goes low when a change of status is detected on

the I/O pins.

SLIC CONTROL INTERFACE

The device provides 12 I/O pins plus 4 CS signals.

The interface can work in dynamic or static mode: it

can be selected by means of DIR register.

Dynamic Mode: the I/O pins are configured as

input or output by means of DIR register. The

CS signals are used to select the different SLIC

interface. In this case the I/O pin can be multi-

plexed. The data loaded from SLIC#n via I/O

pins configured as input can be read in the

DATAn register. The data written in a DATAn

as output when the Csn signal will be active.

Static Mode: The CS signal can be used as I/O

pins. They can be configured as input or out-

put I/O by means of DATA1 register. The data

corresponding to the CS signal can be read or

written by means of DATA2 register. All data

related to th other I/O pins can be read or writ-

ten by means of DATA0 register.

REGISTERS ADDRESSES (only MCU mode)

Addr.

Name

Description

00h

CONF

Configuration Register

01h

DIR-L

I/O Direction (bit 7-0)

02h

DIR-H

I/O Direction (bit 11-8)

03h

DATA0-L

I/O Data ch#0/ Static Data;

(bit 7-0)

04h

DATA0-H

I/O Data ch#0/ Static Data ;

(bit 11-8)

05h

DATA1-L

I/O Data ch#1 (bit 7-0) / CS

Direction

06h

DATA1-H

I/O Data ch#1 (bit 11-8)

07h

DATA2-L

I/O Data ch#1 (bit 7-0) / CS

Data

08h

DATA2-H

I/O Data ch#2 (bit 11-8)

09h

DATA3-L

I/O Data ch#3 (bit 7-0)

0Ah

DATA3-H

I/O Data ch#3 (bit 11-8)

0Bh

GTX0

Transmit Gain ch#0

0Ch

GTX1

Transmit Gain ch#1

0Dh

GTX2

Transmit Gain ch#2

0Eh

GTX3

Transmit Gain ch#3

0Fh

GRX0

Receive Gain ch#0

10h

GRX1

Receive Gain ch#1

11h

GRX2

Receive Gain ch#2

12h

GRX3

Receive Gain ch#3

13h

DXA0

Transmit Timeslot ch#0

14h

DXA1

Transmit Timeslot ch#1

15h

DXA2

Transmit Timeslot ch#2

16h

DXA3

Transmit Timeslot ch#3

17h

DRA0

Receive Timeslot ch#0

18h

DRA1

Receive Timeslot ch#1

19h

DRA2

Receive Timeslot ch#2

1Ah

DRA3

Receive Timeslot ch#3

1Bh

PCMSH

PCM Shift Register

1Ch

DMASK-L

Interrupt Mask I/O Port (03h)

1Dh

DMASK-H

Interrupt Mask I/O Port (04h)

1Eh

CMASK

Interrupt Mask I/O Port (07h)

1Fh

PCHK-A

Persistency Check Time for

Input A

20h

PCHK-B

Persistency Check Time for

Input B

21h

INT

Interrupt Register

22h

ALARM

Alarm Register

23h

AMASK

Interrupt Mask for Alarm

24h

LOOPB

Loopback Register

25h

TXG

Transmit preamp. Gain

26h

RXG-1,0

Receive preamp. Gain (ch1 ch0)

27h

RXG-3,2

Receive preamp. Gain (ch3 ch2)

31h

SRID

Silicon revision identification

code

STLC5046

10/27

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