12345

67

16

17

tHMF

MCLK

tRM

tFM

tWMH

tWML

tSFM

12345

6

7

16

tDMD

FS

DX

tDMZ

12345

6

7

16

tSDM

tHMD

DR

D98TL388C

tXDP

TSX

tDZC

Figure 6c. MCU Mode Frame Sync. Timing.

ELECTRICAL CHARACTERISTICS (continued)

SERIAL CONTROL PORT TIMING

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Frequency of CCLK

4.096

MHz

Period of CCLK high

100

ns

Period of CCLK low

100

ns

Rise Time of CCLK

20

ns

Fall Time of CCLK

20

ns

Hold Time, CCLK high to CS– low

5

ns

Setup Time, CS– low to CCLK high

10

ns

Setup Time, CI valid to CCLK high

20

10

ns

Hold Time, CCLK high to CI

invalid

10

ns

Delay Time, CCLK low to CO

data valid

30

ns

Delay Time, CS–low to CO data

valid

20

ns

(1)

Delay Time CS–high or 8th

CCLK low to CO high impedance

whichever comes first

Pull up resistor = 1k

Ω

50

ns

Hold Time, 8th CCLK high to

CS– high

10

ns

Set up Time, CS– high toCCLK high

10

ns

(1) It is defined as the time at which the output achivies the off state.

STLC5046

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