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STLC5046 数据表(PDF) 20 Page - STMicroelectronics |
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STLC5046 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 27 page ![]() ELECTRICAL CHARACTERISTICS (Typical value 25 °C and nominal supply voltage. Minimum and maximum value are guaranteed over the tem- perature 0 to 70 °C range by production testing and supply voltagerange shown in the Operating Ranges. Per- formances over -40 to +85 °C are guaranteedby productcharacterisationunlessotherwise specified.) DIGITAL INTERFACE Symbol Parameter Test Condition Min. Typ. Max. Unit Vil Input Voltage Low DI pins 0 0.2VDD V Vih Input Voltage High DI pins (1) 0.8VDD 5.5 V Iil Input Current Low DI pins -10 10 µA Iih Input Current High DI pins -10 10 µA Ci Input Capacitance (all dig. inp.) 5 pF Vol Output Voltage Low DX, TSX pins Iol = 3.2mA (other pins Iol = 1mA) 0 0.4 V Voh Output Voltage High DX pinn Ioh = -3.2mA (other pins Iol = 1mA) 0.85VDD VDD V ANALOG INTERFACE RIX Transmit Input Amplifier Input Impedance (VFXI) 1000 M Ω ROR Receive Output Impedance (-1.0V< VFRO<1.0V,IVFRO= 1mA 1 Ω POWER DISSIPATION Idd (pd) Power down Current 9 11 mA Idd Active Current 48 60 mA MASTER CLOCK TIMING fMCLK Frequency of MCLK frequency is automatically detected 1.536 1.544 2.048 4.096 8.192 MHz MHz MHz MHz MHz tWMH Period of MCLK high Measured from VIH to VIH 40 ns tWML Period of MCLK low Measured from VIL to VIL 40 ns tRM Rise Time of MCLK Measured from VIL to VIH 15 ns tFM Fall Time of MCLK Measured from VIH to VIL 15 ns PCM INTERFACE TIMING tHMF Hold Time MCLK low to FS low 10 ns tSFM Setup Time, FS high to MCLK low 10 ns tDMD Delay Time, MCLK high to data valid 10 ns tDMZ (2) Delay Time, MCLK low to DX disabled Pull up resistor = 1k Ω Cload = 30pF 540 ns tSDM Setup Time, DR valid to MCLK low 15 ns tHMD Hold Time, MCLK low to DR invalid 5ns tDZC (2) Delay Time, MCLK low to TSX high Pull up resistor = 1k Ω Cload = 30pF 40 ns tXDP Delay Time, MCLK high to TSX low 10 ns (1) All the digital input are five-volt tollerant - maximum DC voltage 5.5V - maximum peak voltage 6.5V (2) It is defined as the time at which the output achivies the off state. STLC5046 20/27 |
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