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STLC5046 数据表(PDF) 18 Page - STMicroelectronics

部件名 STLC5046
功能描述  PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
PDF  27 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC5046 数据表(HTML) 18 Page - STMicroelectronics

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MCF=1: The corresponding alarm bit (CKF)
doesn’t generate interrupt.
MCF=0: The corresponding alarm bit (CKF) gen-
erates interrupt.
Pin strap value (value=00h):
1
Loopback Register (LOOPB)
Addr=24h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DL3
DL2
DL1
DL0
AL3
AL2
AL1
AL0
DL3..0=0: Normal Operation
DL3..0=1: Codec #3..0 is set in Digital Loopback
mode, this means that the receive PCM
signal applied to the programmed
Receive Time Slot is transferred to the
programmed Transmit Time Slot.
AL3..0=0: Normal Operation
AL3..0=1: Codec #3..0 is set in Analog Loopback
mode, this means that the VFRO signal
is tranferred to the VFXI input internally
into the Codec.
When loopbacks are enabled the signal appears
also at the corresponding VFRO output. It is pos-
sible to have no signal on the VFRO output pro-
gramming the GR register to 00h in case of digital
loopback.
Pin strap value (value=00h):
000
00
00
0
Transmit Preamplifier Gain Register (TXG)
Addr=25h; Reset Value=X0h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
XG3
XG2
XG1
XG0
XG3..0=0:Transmit preamplifier gain ch. 3..0= 0dB
XG3..0=1:Transmit preamplifier gainch. 3..0= 3.52dB
Overall transmit gain depends on combination of
TXG and GTXn registers. For XGn=0 and
GTXn=FF 0dBm0 at DX output correspond to -
15dBm|600Ω (137mVrms) at VFXI input.
Pin strap value (value=00h):
0
000
Receive Amplifier Gain Registers (RXG-10/32)
Addr: 26h; Reset Value=00h
Addr: 27h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R12
R11
R10
R02
R01
R00
R32
R31
R30
R22
R21
R20
Rn2
Rn1
Rn0
Receive Amplifier Gain
Ch#n (dB)
000
Mute
0
0
1
-13.98
0
1
0
-7.96
0
1
1
-4.44
1
0
0
-1.94
101
0
110
0
111
0
Overall receive gain depends on the receive am-
plifier gain (Rn2..0 setting in RXG reg.) and
digital gain (GRXn reg. setting).
As a reference : when Rn2..0 is set for 0dB gain
and GRXn=FFh (max. gain) 0dBm0 at DR input
correspond to a level at VFRO output equal to
547mVrms (e.g. -3dBm 600ohm)
Pin strap value :
Rn2
Rn1
Rn0
GRn = 1
1
1
1
GRn = 0
1
0
0
Overall gain including also GRXn;
GRn = 1: -0.8dB; GRn = 0: -4.3dB.
Silicon Revision Identification Code (SR=D)
Addr: 31h; Read Only.
XX
XX
0
0
0
0
STLC5046
18/27



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