STLC5046 datasheet(17/27 Pages) STMICROELECTRONICS

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Input lines with persistency check generate inter-

rupt if the changed status remains stable longer

than the

time programmend in the persistency

check registers PCHKA/B

Lines without persistency check generate an im-

mediate interrupt request.

Mask register has no effect on those pins config-

ured as outputs, those pins will not generate in-

terrupt.

Pin strap value (value=00h):

111

Persistency Check Register (PCHK-A/B)

Two input signals per channel , labeled A and B,

are submitted to persistency check.

In dynamic mode (STA=0), A and B inputs of the

four channels, are sampled on the multiplexed

lines IO0 (pin13) and IO1 (pin14).

In static mode (STA=1) the persistency check is

performed on four pairs of lines, assigned to

each channel according to the table:

CHAN#

Input A

Input B

IO0 (pin 13)

IO1 (pin 14)

IO4 (pin 17)

IO5 (pin 18)

IO6 (pin 48)

IO7 (pin 47)

IO10 (pin 44)

IO11 (pin 43)

Addr=1Fh;

Reset Value=00h

Addr=20h;

Reset Value=00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

TA7

TA6

TA5

TA4

TA3

TA2

TA1

TA0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

TA7..0 and TB7..0, content of PCHKA and

PCHKB registers, define the minimum duration

of input A and B to generate interrupt ; spurious

transitions shorter than the programmed value

are ignored.

The time width can be calculated according to

the formula:

Time-Width A = (TA7..0) x 64

µs

Time-Width B = (TB7..0) x 64

µs

If PCHKA/B is programmed to 00h the persist-

ency check is not performed and any detected

transition will generate interrupt.

All the inputs, with or without persistency check,

are sampled with a repetition rate of 32

µs

Pin strap value:

000

Interrupt Register (INT)

Addr=21h; Reset Value=00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ICKF

ID3

ID2

ID1

ID0

ICKF = 1: If interrupt is generated by a change of

bit 0 in register ALARM.

In dynamic I/O configuration

the ID3..0

bits

latch the interrupt request from the related chan-

nel.

Any single bit IDn is cleared after reading related

I/O register or by setting MCn bit High (i.e. when

channel n is disabled to generate interrupt ).

In static I/O configuration ID0 and ID2 bits latch

the interrupt request from I/O11..0 and CS3..0 re-

spectively:

ID0 : is set High when the interrupt is requested

from any the I/O11..0 lines.

ID2: is set High when the interrupt is requested

from any of the CS3..0 (configured as I/O).

ID0 and ID2 are cleared after reading related I/O

ID1 and ID3 are don’t care.

Pin strap value (value=00b):

000

Alarm Register (ALARM)

Addr=22h; Reset Value=00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

POR

CKF

CKF=1: If number of PCM clock pulses in one

frame period does not match expected value.

POR=1: If a Power On Reset is detected during

operation.

The register ALARM is cleared after reading op-

eration only if signals are inactive.

Pin strap value (value=00h):

Interrupt Mask Register for Alarm (AMASK)

Addr=23h; Reset Value=11b

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

MCF

STLC5046

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