STLC5046 datasheet(9/27 Pages) STMICROELECTRONICS

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DX represent the transmit PCM interface. It re-

mains in high impedance state except during the

assigned time slots during which the PCM data

byte is shifted out on the rising edge of MCLK.

The four channels can be shifted out in any pos-

sible timeslot as defined by the DXA0 to DXA3

registers. If one codec is set in Power Down by

software programming the corresponding timeslot

is set in High Impedance. When linear coding

mode is selected by CONF register programming

the output channel will need two consecutive

timeslots (see register description).

DR represent the receive PCM interface. It re-

mains inactive except during the assigned time

slots during wich the PCM data byte is shifted in

on the falling edge of MCLK. The four channels

are shifted in any possible timeslot as defined by

the DRA0 to DRA3 registers.

Pin Strap Mode

When pinstrap mode is selected,

dedicated

Frame Sync. FS3..0 are provided on dual func-

tion pins:

MCU

Pin-strap

FS0

IO4

FS1

IO5

FS2

IO6

FS3

The PCMSH register cannot be accessed, there-

fore the beginning of the transmit and receive

frame is identified by the rising edge of the FSn

signal.

Each channel has its dedicated Frame Sync. sig-

nal FSn. Short or Long frame timing is automat-

ically selected; depending on the FS signal ap-

plied to FS0 input. The assigned Time Slot

(Transmit and Receive) takes place in the 8

MCLK cycles following the falling edge of FSn in

case of Short Frame or the rising edge in case of

Long Frame. If one codec is set in Power Down

by proper pin strap configuration the correspond-

ing timeslot is not loaded and the VFRO output is

kept at steady AGND level.

Finally by means of the LOOPB register is possi-

ble to implement a digital or analog loopback on

any of the selected channels.

TSX represent the Transmit Time Slot (open

drain output, 3.2mA). Normally it is floating in

high impedance state except when a time slot is

active on the DX output. In this case TSX output

pulls low to enable the backplane line driver.

Should be strapped to VSS when not used.

CONTROL INTERFACE

STLC5046 has two control modes, a microproc-

essor control mode and a pin strap control mode.

The two modes are selected by M0 and M1 pins.

When M0 = low, M1 = high (MCU control mode)

the MCU port is activated; and the 41 registers of

the device can be programmed. When M0 = high,

M1 = low (Pin-strap mode) the microprocessor

control port is disabled and some of the digital

pins change their function allowing to perform a

very basic programming of the device.

D7..................D0

D7...................D0

Receive /Transmit

Time Slot

TS23/31/61/127

D7...................D0

FS0

FSn

FSm

CH0

CHn

CHm

Figure 4. Pin Strap mode: Time Slot Assignment

Table 1. Control byte structure.

First Byte (Address)

765

210

R/W

D/S

R/W = 0: Write Register

R/W = 1: Read Register

D/S = 0: Single byte

D/S = 1: Two bytes

A5..A0: Register Address

STLC5046

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