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STLC5466 数据表(PDF) 126 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 126 Page - STMicroelectronics |
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126 / 130 page  STLC5466 126/130 4.8 68020; MOD0 = 0, MOD1 = 0, MOD2 = 2 Figure 4-16: 68020 read cycle tx Parameter T min T max Unit t1 Delay NDSACK /NCS0/1 (if t3>t1), (30 pF) Delay when immediate access 0 98 ns ns t2 Hold time Chip Select / NDS rising edge 0 ns t3 Delay NDSACK1 /NDS falling edge (if t1>t3), (30 pF) Delay when immediate access 0 98 ns ns t4 Delay NDSACK1 /NDS rising edge 20 ns t5 Set up time Address and R/W/last NDS or NCS 0 ns t6 Hold time Address /NDS 0 ns t7 Data valid before NDSACK1falling edge (30 pF) 0 15 ns t8 Data High Impedance after NDS (30 pF) 0 15 ns NCS0/1 NDSACK0/ NDTACK NDSACK1/ READY NAS / ALE NDS /NRD SIZE0/ NLDS SIZE1/ NUDS A 0/23 R/W / NWR D0/15 t1 t2 t5 t6 t4 t7 t3 t8 |
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