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STLC5466 数据表(PDF) 127 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 127 Page - STMicroelectronics |
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127 / 130 page ![]() 127/130 STLC5466 Figure 4-17: 68020 write cycle tx Parameter T min T max Unit t1 Delay NDTACK /NCS0/1 (if t3>t1), (30 pF) Delay when immediate access 0 98 ns ns t2 Hold time Chip Select / NDS rising edge 0 ns t3 Delay NDSACK1 /NDS falling edge (if t1>t3), (30 pF) Delay when immediate access 0 98 ns ns t4 Delay NDSACK1 /NDS rising edge 20 ns t5 Set up time Address and R/W/last NDS or NCS 0 ns t6 Hold time Address /NDS 0 ns t9 Set up time Data /NDS 0 ns t10 Hold time Data /NDS 7 ns NCS0/1 NDSACK0/ NDTACK NDSACK1/ READY NAS / ALE NDS /NRD SIZE0/ NLDS SIZE1/ NUDS A 0/23 R/W / NWR D0/15 t1 t2 t5 t6 t4 t9 t10 t3 |
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