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STE2002 数据表(PDF) 14 Page - STMicroelectronics |
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STE2002 数据表(HTML) 14 Page - STMicroelectronics |
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14 / 61 page ![]() Display data RAM STE2002 14/61 Figure 8. Automatic data RAM writing sequence with V=1 and Data RAM mirrored format (MX=1)(a) Figure 9. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=0) Figure 10. Automatic data RAM writing sequence with X-Y carriage return (V=1; MX=0) Figure 11. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=1) 127 126 125 124 3 2 1 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 0 BANK 1 BANK 2 Y CARR BANK 11 BANK 12 0123 124 125 126 127 X CARR BANK 0 BANK 1 BANK 2 Y CARR BANK 11 BANK 12 0123 124 125 126 127 X CARR BANK 0 BANK 1 BANK 2 Y CARR BANK 11 BANK 12 0 1 2 3 124 125 126 127 X CARR |
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