STE2002 datasheet(24/61 Pages) STMICROELECTRONICS

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Bus interfaces

STE2002

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Bus interfaces

To provide the widest flexibility and ease of use the STE2002 features three different

methods for interfacing the host Controller. To select the desired interface the SEL1 and

SEL2 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect

to VDD). All the I/O pins of the unused interfaces must be connected to GND.

All interfaces are working while the STE2002 is in Power Down

5.1

I2C interface

The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast

(400kHz Clock) and High Speed Mode (3.4MHz).

This bus is intended for communication between different Ics. It consists of two lines: one bi-

directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL

lines must be connected to a positive supply voltage via an active or passive pull-up.

The following protocol has been defined:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is high.

Changes in the data line

while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

BUS not busy: Both data and clock lines remain High.

Start Data Transfer: A change in the state of the data line, from High to Low, while the clock

is High, define the START condition.

Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock

signal is High, defines the STOP condition.

Data Valid: The state of the data line represents valid data when after a start condition, the

data line is stable for the duration of the High period of the clock signal. The data on the line

may be changed during the Low period of the clock signal. There is one clock pulse per bit

of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and the stop conditions is not

limited. The information is transmitted byte-wide and each receiver acknowledges with the

ninth bit.

Table 9.

Bus interface

SEL2

SEL1

Interface

Note

I2C

Read and Write; Fast

and High Speed Mode

Serial

Read and Write

Parallel

Read and Write

Not Used

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