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STE2002 数据表(PDF) 15 Page - STMicroelectronics |
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STE2002 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 61 page ![]() STE2002 Display data RAM 15/61 Figure 12. Automatic data RAM writing sequence with X-Y carriage return (V=1; MX=1) Figure 13. Data RAM Byte organization with D0 = 0 Figure 14. Data RAM Byte organization with D0 = 1 Figure 15. Memory rows vs. row drivers mapping with MY=0, MUX81, icon mode=0,1 BANK 0 BANK 1 BANK 2 Y CARR BANK 11 BANK 12 0 1 2 3 124 125 126 127 X CARR 0 MSB LSB 1 2 3 124 125 126 127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 0 LSB MSB 1 2 3 124 125 126 127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 ROW 0 ROW 1 ROW 2 ROW 3 R 3 R 2 R 1 R 0 R 80 ROW 80 0 PHYSICAL MEMORY ROW 1 2 3 124 125 126 127 ICON ROW R 79 Y-CARRIAGE ROW 79 R 3 R 2 R 1 R 0 R 80 R 79 ICON ROW DRIVER ROW DRIVER ICON MODE=1 ICON MODE=0 |
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