STE2002 datasheet(47/61 Pages) STMICROELECTRONICS

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STE2002

Electrical characteristics

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6.3

AC operation

VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5V; Tamb = 25°C;

unless otherwise specified.

Table 27.

AC operation

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Internal oscillator (

Figure 47)

FOSC

Internal oscillator

frequency

VDD = 2.8V;

kHz

FEXT

External oscillator

frequency

100

kHz

FFRAME

Frame frequency

fosc or fext = 72 kHz(1)

Tw(RES)

RES LOW pulse width

µs

Reset pulse rejection

µs

TLOGIC

(RES)

Internal logic reset time

µs

TVDD

VDD1 vs. VDD2 delay

µs

I2C Bus interface(4) (

Figure 48)

FSCL

SCL clock frequency

Fast Mode

400

kHz

High Speed Mode;

Cb=100pF

(max);VDD1=2

3.4

MHz

High Speed Mode;

Cb=400pF (max);

VDD1=2

1.7

MHz

Fast Mode; VDD1=1.7V

400

KHz

TSU;STA

Set-up time (repeated)

START condition

Cb=100pF(2) (3)

160

THD;STA

Hold time (repeated)

START condition

Cb=100pF(2) (3)

160

TLOW

LOW period of the SCLH

clock

Cb=100pF (2) (3)

160

THIGH

HIGH period of the

SCLH clock

Cb=100pF(2) (3)

TSU;DAT

Data set-up time

Cb=100pF (2) (3)

THD;DAT

Data hold time

Cb=100pF (2) (3)

Tr;CL

Rise time of SCLH signal Cb=100pF (2) (3)

TrCL1

Rise time of SCLH signal

after a repeated START

condition and after an

acknowledge bit

Cb=100pF (2) (3)

TfCL

Fall time of SCLH signal

Cb=100pF (2) (3)

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