STE2002 datasheet(26/61 Pages) STMICROELECTRONICS

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Bus interfaces

STE2002

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5.1.1

Communication protocol

The STE2002 is an I2C slave. The access to the device is bi-directional since data write and

status read are allowed.

Four are the device addresses available for the device. All have in common the first 5 bits

(01111). The two least significant bit of the slave address are set by connecting the SA0 and

SA1 inputs to a logic 0 or to a logic 1.

To start the communication between the bus master and the slave LCD driver, the master

must initiate a START condition. Following this, the master sends an 8-bit byte, shown in Fig.

30, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device select

Code, and the 1-bit Read/Write Designator (R/W).

All slaves with the corresponding address acknowledge in parallel, all the others will ignore

the I2C-bus transfer.

Writing mode

If the R/W bit is set to logic 0 the STE2002 is set to be a receiver. After the slaves

acknowledge one or more command word follows to define the status of the device.

A command word is composed by two bytes. The first is a control byte which defines the Co

and D/C values, the second is a data byte (fig 31). The Co bit is the command MSB and

defines if after this command will follow one data byte and an other command word or if will

follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines

whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C = 0 Command).

If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and

D/C =1, the following data byte will be stored in the data RAM at the location specified by the

data pointer.

Every byte of a command word must be acknowledged by all addressed units.

After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside

the STE2002 Display RAM starting at the address specified by the data pointer. The data

pointer is automatically updated after every byte written and in the end points to the last

RAM location written.

Every byte must be acknowledged by all addressed units.

Reading mode

If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If

the D/C bit sent during the last write access, is set to a logic 0, the byte read is the status

byte.

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