STE2002 datasheet(27/61 Pages) STMICROELECTRONICS

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STE2002

Bus interfaces

27/61

Figure 30.

Communication protocol

5.2

Serial interface

The STE2002 serial Interface is a bidirectional link between the display driver and the

application supervisor.

It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one

for the peripheral enable (SCE) and one for mode selection (SD/C).

The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the

serial peripheral power consumption is zero. While SCE pin is high the serial interface is

kept in reset.

The STE2002 is always a slave on the bus and receive the communication clock on the

SCLK pin from the master.

Information are exchanged byte-wide. During data transfer, the data line is sampled on the

positive SCLK edge.

SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C

=1);it is read on the eighth SCLK clock pulse during every byte transfer.

If SCE stays low after the last bit of a command/data byte, the serial interface expects the

MSB of the next byte at the next SCLK positive edge.

A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM

and all the internal registers are cleared.

If SCE is low after the positive edge of RES, the serial interface is ready to receive data.

Throughout SOUT can be read only the driver I2C slave address. The Command sequence

that allows to read I2C slave address is reported in Fig. 34 & 35. SOUT is in High impedance

in steady state and during data write.

It is possible to short circuit DOUT and SDIN and read I2C address without any additional

lines.

01111

A0A

STE2002 ACK

WRITE MODE

READ MODE

R/W

SLAVE ADDRESS

STE2002 ACK

COMMAND WORD

CONTROL BYTE

MSB........LSB

LAST

N> 0 BYTE

STE2002 ACK

1 DC Control Byte

DATA Byte

DC Control Byte

A 0

DATA Byte

A P

01111

A1A

STE2002 ACK

MASTER ACK

STE2002

SLAVE ADDRESS

01111

CONTROL BYTE

000000 A

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