STE2002 datasheet(25/61 Pages) STMICROELECTRONICS

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STE2002

Bus interfaces

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By definition, a device that gives out a message is called "transmitter", the receiving device

that gets the signals is called "receiver". The device that controls the message is called

"master". The devices that are controlled by the master are called "slaves"

Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This

acknowledge bit is a low level put on the bus by the receiver, whereas the master generates

an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also, a master receiver must generate an acknowledge after the reception of

each byte that has been clocked out of the slave transmitter. The device that acknowledges

has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and

hold time must be taken into account. A master receiver must signal an end-of-data to the

slave transmitter by not generating an acknowledge on the last byte that has been clocked

out of the slave. In this case, the transmitter must leave the data line High to enable the

master to generate the STOP condition.

Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.

Having the acknowledge output (SDAOUT) separated from the serial data line is

advantageous in Chip-On-Glass (COG) applications. In COG applications where the track

resistance from the SDAOUT pad to the system SDA line can be significant, a potential

divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track

resistance. It is possible that during the acknowledge cycle the STE2002 will not be able to

create a valid logic 0 level. By splitting the SDA input from the output the device could be

used in a mode that ignores the acknowledge bit. In COG applications where the

acknowledge cycle is required, it is necessary to minimize the track resistance from the

SDACK pad to the system SDA line to guarantee a valid LOW level.

To be compliant with the I2C-bus Hs-mode specification the STE2002 is able to detect the

special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.

Since no internal modification are applied to work in Hs-mode, the device is able to work in

Hs-mode without detecting the master code.

Figure 28.

Bit transfer and START,STOP conditions definition

Figure 29.

Acknowledgment on the I2C-bus

DATA LINE

STABLE

DATA VALID

CHANGE OF

DATA ALLOWED

START

CONDITION

STOP

CONDITION

CLOCK

DATA

D00IN1151

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

DATA OUTPUT

BY RECEIVER

SCLK FROM

MASTER

DATA OUTPUT

BY TRANSMITTER

D00IN1152

MSB

LSB

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