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AT80C51RA2-RLSIV 数据表(PDF) 68 Page - ATMEL Corporation |
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AT80C51RA2-RLSIV 数据表(HTML) 68 Page - ATMEL Corporation |
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68 / 86 page  68 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 11-8. External Data Memory Read Cycle 11.5.7 Serial Port Timing - Shift Register Mode Table 11-10. AC Parameters for a Fix Clock Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TAVDV TLLAX T RLDV Speed -M 40 MHz -V X2 mode 30 MHz 60 MHz equiv. -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. -L standard mode 30 MHz Units Symbol Min Max Min Max Min Max Min Max Min Max TXLXL 300 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 0 0 0 ns TXHDV 117 34 117 117 200 ns |
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