TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303

system block diagram

1394 Link-

Layer

Controller

Host

Interface

D0 – D1

CTL0 – CTL1

LREQ

SCLK

1394

Backplane

Physical-

Layer

Controller

TSB14C01A

BPdata

BPstrb

NOTE A: The backplane transceiver is customer supplied and is different for each type of backplane.

2

/

2

/

Tdata

Rdata

Rstrb

Tstrb

N_OEB_D

functional block diagram

TSTRB

Sub Act Gap

Cycle Req

Iso Req

LINK/PHY

Interface

SCLK

D0 – D1

CTL0 – CTL1

LREQ

CLK

(see Note A)

Physical ID

Pr0 – Pr3

Fair/Urg Req

Ack Req

Arb Won

Arb Lost

Arb Res Gap

Ack Gap

Bus Reset

CLK

RxData

RxCLK

ARB

Control

Data

Encode

SCLK

D0, D1

Data

Resync/

Decode

CLK

TxArbStrb

TxArbData

RxStb

RxData

CLK

RxCLK

RSTRB

RDATA

ARB/DATA

MUX

TxPktStrb

TxPktData

TDATA

2

/

2

/

NOTE A: CLK is either terminal XI_50 or XI_100 depending on the mode selection.