TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

21

POST OFFICE BOX 655303

Total Transmit Skew

+ Transmit Package Skew ) Spatial Skew ) Logic Skew

This is given by the following equation.

Total Receive Skew

+ Receive Package Skew ) Spatial Skew ) Receive Setup ) Receive Hold

Skew Margin

+ Bit Cell Period * Total Transmit Skew * Backplane Skew * Total Receive Skew

bus signals to ensure proper operation of data-strobe bit level encoding. Transmit edge separation is

measured from the midpoint of the signal transition to the midpoint of the next signal transition out on the

bus. Minimum transmit edge separation is the minimum bit cell period less the maximum total transmit skew.

bus signals to ensure proper operation of data-strobe bit level decoding. Receive edge separation is

measured from the midpoint of the signal transition to the midpoint of the next signal transition out on the

bus. This is the minimum bit cell period reduced by the amount of maximum total transmit skew and

maximum backplane skew.

gap timing

A gap is a period of time during which the bus is idle (Data_Rx and Strb_Rx are unasserted). There are three

types of gaps:

isochronous transfers. A node should detect the occurrence of an acknowledge gap after the bus has been

in an unasserted state for 4 arbitration clock times (approximately 81.38 ns), but should not assert the bus

until a total of 8 arbitration clock times (approximately 182.76 ns) have occurred. This requirement ensures

that a node is given adequate time to detect the acknowledge gap before the bus is asserted by another

node upon detecting an acknowledge gap. This includes the minimum time required to detect a BUS_IDLE

(4 arbitration clock times), as well as the maximum delay between the arbitration state machines within any

two nodes on the bus (another 4 arbitration clock times).

the occurrence of a subaction gap after the bus has been in an unasserted state for at least 16 arbitration

clock times (approximately 325.52 ns), but should not assert the bus until a total of 20 arbitration clock times

(approximately 406.9 ns) have occurred. This requirement ensures that a node is given adequate time to

detect the subaction gap before the bus is asserted by another node (upon detecting a subaction gap). The

duration of the subaction gap ensures that another node asserting the bus after an acknowledge gap has

been detected by this time.

should detect the occurrence of an arbitration reset gap after the bus has been in an unasserted state for

at least 28 arbitration clock times (approximately 569.66 ns), but should not assert the bus until a total of

32 arbitration clock times (approximately 651.04 ns) have occurred. This requirement ensures that a node

is given adequate time to detect the arbitration reset gap before the bus is asserted by another node (upon

detecting an arbitration reset gap). The duration of the arbitration reset gap ensures that another node

asserting the bus after a subaction gap or an acknowledge gap has been detected by this time.

If a node is waiting for the occurrence of a particular gap, and the bus has become idle for the specified time

(e.g., 32 arbitration clock times for an arbitration reset gap), the node detects the gap and asserts the bus within

the time constraints described under the bus synchronization and propagation delay section of this document.

These constraints ensure that an asserted signal propagates through the node decision/transceiver circuitry

and onto the bus soon enough to allow arbitration to occur properly.