TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

bus request

For fair or priority access, the link requests control of the bus at least one clock after the phy-link interface

becomes idle. When the link senses that the CTL terminals are in a receive state (CTL 0 and CTL1 = 10), then

it knows that its request has been lost. This is true anytime during or after the link sends the bus request transfer.

Additionally, the phy ignores any fair or priority requests if it asserts the receive state while the link is requesting

the bus. The link then reissues the request one clock after the next interface idle.

The cycle master node uses a priority request (PriReq) to send the cycle start message. To request the bus to

send isochronous data, the link can issue the request at any time after receiving the cycle start. The phy clears

an isochronous request only when the bus has been won.

To send an acknowledge, the link must issue an ImmReq request during the reception of the packet addressed

to it. This is required because the delay from end-of-packet to acknowledge request adds directly to the

minimum delay every phy must wait after every packet to allow an acknowledge to occur. After the packet ends,

the phy immediately takes control of the bus and grants the bus to the link. If the header cyclic redundancy check

(CRC) of the packet turns out to be bad, the link releases the bus immediately. The link cannot use this grant

to send another type of packet. To ensure this, the link must wait 160 ns after the end of the received packet

to allow the phy to grant it the bus for the acknowledgement, then releases the bus and proceeds with another

request.

Although highly improbable, it is conceivable that two separate nodes can believe that an incoming packet is

intended for them. The nodes then issue an ImmReq request before checking the CRC of the packet. Since both

phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs somewhere

between the competing nodes. This collision would be interpreted by the other nodes on the network as being

a ZZ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken node drops its request

and the false line state is removed. The only side effect would be the loss of the intended acknowledgment

packet (this is handled by the higher-layer protocol).

Once the link issues an immediate, isochronous, fair, or priority request for access to the bus, it cannot issue

another request until the phy indicates a lost (incoming packet) or won (transmit) signal. The phy ignores new

requests while a previous request is pending.

read/write requests

For write requests, the phy takes the value in the data field (see Table 2) of the transfer and loads it into the

addressed register as soon as the transfer is complete. For read requests (see Table 2), the phy returns the

contents of the addressed register at the next opportunity through a status transfer. The link is allowed to perform

a read or write operation at any time. When the status transfer is interrupted by an incoming packet, the phy

continues to attempt the transfer of the requested register until it is successful.