TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

12

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Table 6. Request Bit Length

Request Type

Number of

Bits

Bus request (cable)

7

Bus request (backplane)

11

Read register request

9

Write register request

17

For a bus request in the cable environment, the length of the LREQ data stream is 7 bits as shown in Table 7.

Table 7. Bus Request For Cable Environment

Bit(s)

Name

Description

0

Start bit

Indicates the beginning of the transfer (always 1).

1-3

Request type

Indicates the type of bus request (see Table 11 for the encoding of this

field).

4-5

Request speed

Indicates the speed at which the phy sends the packet for this request. This

field has the same encoding as the speed code from the first symbol of the

receive packet. See Table 8 for the encoding of this field. This field can be

expanded to support data rates higher than 400 Mbit/s in the future.

6

Stop bit

Indicates the end of the transfer (always 0).

When LREQ transfer is a bus request in the backplane environment, it is 11 bits long and has the format shown

in Table 8.

Table 8. Bus Request For Backplane Environment

Bit(s)

Name

Description

0

Start bit

Indicates the beginning of the transfer (always 1).

1-3

Request type

Indicates the type of bus request (see Table 11 for the encoding of this

field).

4-5

Request speed

Ignored (set to 00) for the backplane environment

6-9

Request priority

Indicates priority of urgent requests. It is only used with a FairReq request

type. All zeros indicates fair request.

All ones is reserved (this priority is implied by a PriReq).

Other values are used to indicate the priority of an urgent request.

10

Stop bit

Indicates the end of the transfer (always 0).

For a Read Register Request the length of the LREQ data stream is 9 bits as shown in Table 9 (also see Table 3

for the bit definitions).

Table 9. Read Request Format

Bit(s)

Name

Description

0

Start bit

Indicates the beginning of the transfer (always 1).

1-3

Request type

Always a 100 indicating that this is a read register request.

4-7

Address

Is the address of the phy register to be read.

8

Stop bit

Indicates the end of the transfer (always 0).