TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

transmit

When the link requests access to the serial bus through the LREQ terminal, the phy arbitrates for access to the

serial bus. When the phy wins the arbitration, it grants the bus to the link by asserting transmit on the CTL

terminals for one SCLK cycle, followed by idle for one cycle. After sampling the transmit state from the phy, the

link takes over control of the interface by asserting either hold or transmit on the CTL terminals. The link asserts

hold to keep ownership of the bus while preparing data. The phy asserts the data-on state on the serial bus

during this time. When it is ready to begin transmitting a packet, the link asserts transmit on the CTL terminals

along with the first bits of the packet. After sending the last bits of the packet, the link asserts either idle or hold

on the CTL terminals for one cycle, and then idle for one additional cycle, before asserting those terminals to

a high-impedance state.

The hold state here indicates to the phy that the link needs to send another packet without releasing the bus.

The phy responds to this hold state by waiting the required minimum time and then asserting transmit as before.

This function would be used after sending an acknowledgement if the link intends to send a unified response,

or to send consecutive isochronous packets during a single cycle. The only requirement when sending multiple

packets during a single bus ownership is that all packets must be transmitted at the same speed, since the speed

of the packet transmission is set before the first packet.

As noted above, when the link has finished sending the last packet for the current bus ownership, it releases

the bus by asserting idle on the CTL terminals for two SCLK cycles. The phy begins asserting idle on the CTL

terminals one clock after sampling the second idle from the link. Note that whenever the D and CTL lines change

ownership between the phy and the link, there is an extra clock period allowed so that both sides of the interface

can operate on registered versions of the interface signals, rather than having to respond to a CTL state on the

next cycle.

It is not required that the link enter the hold state before sending the first packet when implementation permits

the link to be ready to transmit as soon as bus ownership is granted. The timing for a single packet transmit

operation is shown in Figure 6. In the diagram, D0 – Dn are the data symbols of the packet; ZZ represents the

high-impedance state.