ADP2114ACPZ-R7 datasheet(28/40 Pages) AD

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ADP2114

Rev. 0 | Page 28 of 40

The ADP2114 can be configured in either a 2 A/2 A or a 3 A/1 A

current limit configuration and, therefore, the current limit

thresholds for the two channels are different in each setting.

The inductor chosen for each channel must have at least the

peak output current limit of the IC in each case for robust

operation during short-circuit conditions. The following

inductors are recommended:

•

From 0.47 μH to 4.7 μH, the TOKO D53LC and

FDV0620 series

•

From 4.7 μH to 12 μH, the Cooper Bussman DR1050 series

and the Wurth Elektronik WE-PDF series.

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage

ripple and the loop dynamics of the converter. The ADP2114

is designed for operation with small ceramic output capacitors

that have low ESR and ESL; therefore, comfortably able to meet

tight output voltage ripple specifications. X5R or X7R dielectrics

are recommended with a voltage rating of 6.3 V or 10 V. Y5V

and Z5U dielectrics are not recommended due to their poor

temperature and dc bias characteristics. The minimum output

capacitance, COUT_MIN, is determined by Equation 7 and

Equation 8.

For acceptable maximum output voltage ripple,

⎟

⎠

⎞

⎜

⎝

⎛

≅

OUT_MIN

RIPPLE

ESR

ΔI

ΔV

(7)

Therefore,

)

(

—

ESR

ΔI

ΔV

ΔI

RIPPLE

OUT_MIN

≅

(8)

where:

ΔVRIPPLE is allowable peak-to-peak output voltage ripple in volts.

ΔIL is the inductor ripple current.

ESR is the equivalent series resistance of the capacitor in ohms.

fSW is the converter switching frequency in Hertz.

If there is a step load, choose the output capacitor value based

on the value of the step load. For the maximum acceptable

output voltage droop/overshoot caused by the step load,

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

≅

DROOP

OUT_STEP

OUT_MIN

ΔV

ΔI

(9)

where:

ΔIOUT_STEP is the load step value in amperes.

fSW is the switching frequency in Hertz.

ΔVDROP is the maximum allowable output voltage

droop/overshoot in volts for the load step.

Note that the previous equations are approximations and are

based on following assumptions:

•

The inductor value is based on the peak-to-peak current

being 30% of the maximum load current.

•

Voltage drops across the internal MOSFET switches and

across the dc resistance of the inductor are ignored.

•

In Equation 9, it is assumed that it takes up to three switching

cycles until the loop adjusts the inductor current in response

to the load step.

Select the largest output capacitance given by Equation 8 and

Equation 9. While choosing the actual type of ceramic capacitor

for the output filter of the converter, pick one with a nominal

capacitance that is 20% to 30% larger than the calculated value

because the effective capacitance decreases with larger dc voltages.

In addition, the rated voltage of the capacitor must be higher

than the output voltage of the converter.

Recommended input and output ceramic capacitors include

•

Murata GRM21BR61A106KE19L, 10 μF, 10 V, X5R, 0805

•

TDK C2012X5R0J226M, 22 μF, 6.3 V, X5R, 0805

•

Panasonic ECJ-4YB0J476M, 47 μF, 6.3 V, X5R, 1210

•

Murata GRM32ER60J107ME20L, 100 μF, 6.3 V, X5R, 1210

CONTROL LOOP COMPENSATION

The ADP2114 uses a peak, current mode control architecture

for excellent load and line transient response. The external

voltage loop is compensated by a transconductance amplifier

with a simple external RC network between the COMP1

(COMP2) pin and GND, as shown in Figure 77.

VFBx

0.6V

ADP2114

COMPx

RCOMP

CCOMP

CC2

GND

Figure 77. Compensation Components

The basic control loop block diagram is shown in Figure 78.

VCOMP

CCOMP

RCOMP

VREF = 0.6V

VIN

PULSE

WIDTH

MODULATOR

VOUT

INDUCTOR

CURRENT

SENSE

ADP2114

Figure 78. Basic Control Block Diagram

The blocks and components shown enclosed within the dashed line

in Figure 78 are embedded inside each channel of the ADP2114.

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