ADP2114ACPZ-R7 datasheet(30/40 Pages) AD

30 / 40 page

ADP2114

Rev. 0 | Page 30 of 40

DESIGN EXAMPLE

The external component selection procedure from the Control

Loop Compensation section is used for this design example.

Table 9. 2-Channel Step-Down DC-to-DC Converter

Requirements

Parameter

Specification

Additional

Requirements

Input Voltage, VIN

5.0 V ±10%

None

Channel 1, VOUT1

3.3 V, 2 A, 1% VOUT

ripple (p-p)

Maximum load step:

1 A to 2 A, 5% droop

maximum

Channel 2, VOUT2

1.8 V, 2 A, 1% VOUT

ripple (p-p)

Maximum load step:

1 A to 2 A, 5% droop

maximum

Pulse-Skip Feature

Enabled

None

CHANNEL 1 CONFIGURATION AND COMPONENTS

SELECTION

Complete the following steps to configure Channel 1:

For the target output voltage, VOUT = 3.3 V, connect the

V1SET pin through a 47 kΩ resistor to GND (see Table 4).

Because one of the fixed output voltage options is chosen,

the feedback pin (FB1) must be directly connected to the

output of Channel 1, VOUT1.

Estimate the duty-cycle, D, range. Ideally,

OUT

D =

(20)

That gives the duty cycle for the 3.3 V output voltage and

the nominal input voltage of DNOM = 0.66 at VIN = 5.0 V.

The minimum duty cycle, DMIN, for the maximum input

voltage (10% above the nominal) is DMIN = 0.60 at VIN

maximum = 5.5 V

The maximum duty cycle, DMAX, for the minimum input

voltage (10% less than nominal) is DMAX = 0.73 at VIN

minimum = 4.5 V.

However, the actual duty cycle is larger than the calculated

values to compensate for the power losses in the converter.

Therefore, add 5% to 7% at the maximum load.

Based on the estimated duty-cycle range, choose the

switching frequency according to the minimum and

maximum duty-cycle limitations, as shown in Figure 72.

For the Channel 1 VIN = 5 V and VOUT = 3.3 V combination,

choose fSW = 600 kHz with a maximum duty cycle of 0.8.

This frequency option provides the smallest sized solution.

If a higher efficiency is required, choose the 300 kHz option.

However, the PCB footprint area of the converter will be

larger because of the bigger inductor and output capacitors.

Select the inductor by using Equation 5.

OUT

−

)

(

In Equation 5, VIN = 5 V, VOUT = 3.3 V, ΔIL = 0.3 × IL = 0.6 A,

and fSW = 600 kHz, which results in L = 3.11 μH.

Therefore, when L = 3.3 μH (the closest standard value) in

Equation 3, ΔIL = 0.566 A.

Although the maximum output current required is 2 A, the

maximum peak current is 3.3 A under the current limit

condition (see Table 7). Therefore, the inductor should be

rated for 3.3 A of peak current and 3 A of average current

for reliable circuit operation.

Select the output capacitor by using Equation 8 and

Equation 9.

)

(

ESR

ΔI

ΔV

ΔI

RIPPLE

OUT_MIN

≅

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

≅

DROOP

OUT_STEP

OUT_MIN

ΔV

ΔI

Equation 8 is based on the output ripple (ΔVRIPPLE), and

Equation 9 is for capacitor selection based on the transient

load performance requirements that allow, in this case, 5%

maximum deviation. As previously mentioned, perform

these calculations and choose whatever equation yields the

larger capacitor size.

In this case, the following values are substituted for the

variables in Equation 8 and Equation 9:

ΔIL = 0.566 A

fSW = 600 kHz

ΔVRIPPLE = 33 mV (1% of 3.3 V)

ESR = 3 mΩ (typical for ceramic capacitors)

ΔIOUT_STEP = 1 A

ΔVDROOP = 0.165 V (5% of 3.3 V)

The output ripple based calculation (see Equation 8) dictates

that COUT = 4.0 μF, whereas the transient load based

calculation (see Equation 9) dictates that COUT = 30 μF. To

meet both requirements, choose the latter. As previously

mentioned in the Control Loop Compensation section, the

capacitor value reduces with applied dc bias; therefore, select a

higher value. In this case, the next higher value is 47 μF

with a minimum voltage rating of 6.3 V.

Calculate the feedback loop, compensation component

values by using Equation 15.

H(s)

= gM × GCS ×

OUT

REF

× ZCOMP(s) × ZFILT(s)

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