ADP2114ACPZ-R7 datasheet(31/40 Pages) AD

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ADP2114

Rev. 0 | Page 31 of 40

In this case, the following values are substituted for the

variables in Equation 18:

gm = 550 μs

GCS = 4A/V

VREF = 0.6 V

VOUT = 3.3 V

COUT = 0.8 × 47 μF (capacitance derated by 20% to account

for dc bias).

From Equation 18,

RCOMP = 27 kΩ.

Substituting RCOMP in Equation 19 yields CCOMP = 1000 pF.

Table 10. Channel 1 Circuit Settings

Circuit Parameter

Setting

Value

Output Voltage, VOUT

Step 1

3.3 V

Reference Voltage, VREF

Fixed, typical

0.6 V

Error Amp Transconductance, gm

Fixed, typical

550 μs

Current Sense Gain, CCS

Fixed, typical

4 A/V

Switching Frequency, fSW

Step 2

600 kHz

Crossover Frequency, fC

1/12 fSW

50 kHz

Zero Frequency, fZERO

1/8 fCROSS

6.25 kHz

Output Inductor, LOUT

Step 3

3.3 μH

Output Capacitor, COUT

Step 4

47 μF, 6.3 V

Compensation Resistor, RCOMP

Equation 18

27 kΩ

Compensation Capacitor, CCOMP

Equation 19

1000 pF

CHANNEL 2 CONFIGURATION AND COMPONENTS

SELECTION

Complete the following steps to configure Channel 2:

For the target output voltage, VOUT = 1.8 V, connect the

V2SET pin through a 15 kΩ resistor to GND (see Table 4).

Because one of the fixed output voltage options is chosen,

the feedback pin (FB2) must be directly connected to the

output of Channel 2, VOUT2.

Estimate the duty-cycle, D, range (see Equation 20). Ideally,

OUT

D =

That gives the duty cycle for the 1.8 V output voltage and

the nominal input voltage of DNOM = 0.36 at VIN = 5.0 V.

The minimum duty cycle for the maximum input voltage (10%

above the nominal) is DMIN = 0.33 at VIN maximum = 5.5 V.

The maximum duty cycle for the minimum input voltage (10%

less than nominal) is DMAX = 0.4 at VIN minimum = 4.5 V.

However, the actual duty cycle is larger than the calculated

values to compensate for the power losses in the converter.

Therefore, add 5% to 7% at the maximum load.

The switching frequency (fSW) of 600 kHz, which is chosen

based on the Channel 1 requirements, meets the duty cycle

ranges that have been previously calculated. Therefore, this

switching frequency is acceptable.

Select the inductor by using Equation 5.

OUT

−

)

(

In Equation 5, VIN = 5 V, VOUT = 1.8 V, ΔIL = 0.3 × IL =

0.6 A, and fSW = 600 kHz, which results in L = 2.9 μH.

Therefore, when L = 3.3 μH (the closest standard value) in

Equation 3, ΔIL = 0.582 A.

Although the maximum output current required is 2 A, the

maximum peak current is 3.3 A under the current limit

condition (see Table 7). Therefore, the inductor should be

rated for 3.3 A of peak current and 3 A of average current

for reliable circuit operation under all conditions.

Select the output capacitor by using Equation 8 and

Equation 9.

)

(

ESR

ΔI

ΔV

ΔI

RIPPLE

OUT_MIN

≅

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

≅

DROOP

OUT_STEP

OUT_MIN

ΔV

ΔI

Equation 8 is based on the output ripple (ΔVRIPPLE), and

Equation 9 is for capacitor selection based on the transient

load performance requirements that allow, in this case, 5%

maximum deviation. As mentioned earlier, perform these

calculations and choose whatever equation yields the larger

capacitor size.

In this case, the following values are substituted for the

variables in Equation 8 and Equation 9:

ΔIL = 0.582 A

fSW = 600 kHz

ΔVRIPPLE = 18 mV (1% of 1.8 V)

ESR = 3 mΩ (typical for ceramic capacitors)

ΔIOUT_STEP = 1 A

ΔVDROOP = 0.09 V (5% of 1.8 V)

The output ripple based calculation (see Equation 8) dictates

that COUT = 7.7 μF, whereas the transient load based

calculation (see Equation 9) dictates that COUT = 55 μF. To

meet both requirements, choose the latter. As previously

mentioned in the Control Loop Compensation section, the

capacitor value reduces with applied dc bias; therefore, select

a higher value. In this case, choose a 47 μF/6.3 V capacitor

and a 22 μF/6.3 V capacitor in parallel to meet the

requirements.

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