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ADP2114ACPZ-R7 数据表(PDF) 20 Page - Analog Devices |
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ADP2114ACPZ-R7 数据表(HTML) 20 Page - Analog Devices |
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20 / 40 page  ADP2114 Rev. 0 | Page 20 of 40 SIMPLIFIED BLOCK DIAGRAM THERMAL SHUTDOWN OTSD VDD UVLO UVLO GND HICCUP TIMER GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOT THROUGH PROTECTION SLOPE COMPENSATION/ RAMP GENERATOR VOUT SELECTOR UVLO OSC_CH1 PULSE SKIP ENABLE OTSD SCFG OPCFG EN1 COMP1 FREQ SYNC/CLKOUT OSC PHASE SHIFT CURRENT LIMIT/ CONFIGURATION OSC_CH1 OSC_CH2 CLIM_CH1 CLIM_CH2 PULSE SKIP ENABLE PGOOD1 VFB1 0.7V 0.5V SW1 VIN1 VIN2 VIN3 SW2 PGND1 PGND2 PMOS NMOS PWM COMPARATOR CURRENT LIMIT COMPARATOR CURRENT SENSE AMPLIFIER CHANNEL 1 CLIM_CH1 V1SET FB1 – + + VFB1 gm ERROR AMPLIFIER VREF = 0.6V VDD ISS = 6µA – + POWER STAGE SS1 HICCUP TIMER GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOT THROUGH PROTECTION SLOPE COMPENSATION/ RAMP GENERATOR VOUT SELECTOR UVLO OSC_CH2 PULSE SKIP ENABLE OTSD EN2 COMP2 PGOOD2 VFB2 0.7V 0.5V SW3 VIN4 VIN5 VIN6 SW4 PGND3 PGND4 PMOS NMOS PWM COMPARATOR CURRENT LIMIT COMPARATOR CURRENT SENSE AMPLIFIER CHANNEL 2 CLIM_CH2 V2SET FB2 – + + VFB2 gm ERROR AMPLIFIER VREF = 0.6V VDD ISS = 6µA – + POWER STAGE SS2 Figure 65. Simplified Block Diagram |
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