ADP2114

Rev. 0 | Page 7 of 40

Pin No.

Mnemonic

Description

14

VIN4

Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.

15

VIN5

Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.

16

VIN6

Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.

17

SW4

Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.

Tie SW3 to SW4 and then connect the output LC filter between SW and the output voltage.

18

SW3

Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.

Tie SW3 to SW4 and then connect the output LC filter between SW and the output voltage.

19

PGND4

Power Ground. Source of the low-side internal power MOSFET of Channel 2.

20

PGND3

Power Ground. Source of the low-side internal power MOSFET of Channel 2.

21

PGND2

Power Ground. Source of the low-side internal power MOSFET of Channel 1.

22

PGND1

Power Ground. Source of the low-side internal power MOSFET of Channel 1.

23

SW2

Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.

Tie SW1 to SW2 and connect the output LC filter between SW and the output voltage.

24

SW1

Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.

Tie SW1 to SW2 and connect the output LC filter between SW and the output voltage.

25

VIN3

Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.

26

VIN2

Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.

27

VIN1

Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.

28

EN1

Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter and drive EN1 low to turn off

Channel 1. Tie EN1 to VDD for startup with VDD. With multiphase configurations, connect EN1 to EN2.

29

PGOOD1

Open-Drain Power Good Output for Channel 1. Place a 100 kΩ pull-up resistor to VDD or any other voltage ≤ 5.5 V;

PGOOD1 pulls low when Channel 1 is out of regulation.

30

SS1

Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor

sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2.

31

V1SET

Output Voltage Set Pin for Channel 1. Connect this pin through a resistor to GND or tie to VDD to select a fixed

for output voltage selection.

32

FB1

EPAD (EP)

Exposed Thermal Pad. Connect to the signal/analog ground plane.