ADP2114ACPZ-R7 datasheet(22/40 Pages) AD

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ADP2114

Rev. 0 | Page 22 of 40

The capacitance value of the soft start capacitor defines the soft

start time, tSS, based on

REF

(1)

where:

VREF is the internal reference voltage, 0.6 V.

ISS is the soft start current, 6 μA.

CSS is the soft start capacitor value.

If the output voltage VOUT1 (VOUT2) is precharged prior to enabling

Channel 1 (Channel 2), the control logic prevents inductor

current reversal by holding the power MOSFETs off until the

soft start voltage ramp at SS1 (SS2) reaches the precharged

output voltage on VFB1 (VFB2), see Figure 67.

CH3 5.0V

CH2 1.0V

CH1 5.0V

CH4 500mV

M200µs

A CH1

2.4V

ENx

VOUT

SSx

Figure 67. Start with a Precharged Load

POWER GOOD

The ADP2114 features open-drain, power-good outputs

(PGOOD1 and PGOOD2) that indicate when the converter

output voltage is within regulation. The power good signal

transitions low immediately when the corresponding channel is

disabled.

The power good circuitry monitors the output voltage on the

FB1 (FB2) pin and compares it to the rising and falling

thresholds shown in Table 1. If the output voltage, VOUT1

(VOUT2), exceeds the typical rising limit of 116% of the target

output voltage, VOUT1SET (VOUT2SET), the PGOOD1 (PGOOD2)

pin pulls low. The PGOOD1 (PGOOD2) pin continues to pull

low until the output voltage recovers down to 108% (typical) of

the target value.

If the output voltage drops below 84% of the target output voltage,

the corresponding PGOOD1 (PGOOD2) pin pulls low. The

PGOOD1 (PGOOD2) pin continues to pull low until the output

voltage rises to within 92% of the target output voltage. The

PGOOD1 (PGOOD2) pin then releases and signals the return

of the output voltage within the power good window.

The power good thresholds are shown in Figure 68. The PGOOD1

and PGOOD2 outputs also sink current if an overtemperature

condition is detected. Use these outputs as logical power good

signals by connecting the pull-up resistors from PGOOD1

(PGOOD2) to VDD. If the power good function is not used, the

pins can be left floating.

108%

92%

116%

84%

100%

PGOOD1

(PGOOD2)

VOUT FALLING

VOUT RISING

POWER

GOOD

OVERVOLTAGE

UNDERVOLTAGE

POWER

GOOD

Figure 68. PGOOD1 and PGOOD2 Thresholds

PULSE SKIP MODE

The ADP2114 has built-in, pulse skip circuitry that turns on

during light loads, switching only as necessary to maintain the

output voltage within regulation. This allows the converter to

maintain high efficiency during light load operation by reducing

the switching losses. The pulse skip mode can be selected by

configuring the OPCFG pin according to Table 7. In pulse skip

mode, when the output voltage dips below regulation, the

ADP2114 enters PWM mode for a few oscillator cycles to

increase the output voltage back to regulation. During the

wait time between bursts, both power switches are off, and the

output capacitor supplies all load current. Because the output

voltage dips and recovers occasionally, the output voltage ripple

in this mode is larger than the ripple in the PWM mode of

operation.

If the converter is configured to operate in forced PWM mode

(by selecting that configuration on the OPCFG pin), the device

operates with a fixed switching frequency, even at light loads.

ADP2114ACPZ-R7 数据表(PDF) 22 Page - Analog Devices

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