ADP2114ACPZ-R7 datasheet(26/40 Pages) AD

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ADP2114

Rev. 0 | Page 26 of 40

OPERATION MODE CONFIGURATION

The dual-channel ADP2114 can be configured to one of the four

modes of operation by connecting the OPCFG pin as shown in

Table 7. This configuration sets the current limit for each

channel and enables or disables the transition to pulse skip mode

at light loads.

In the dual-phase configuration, the outputs of the two channels

are connected together, and they generate a single dc output

voltage, VOUT. For this single combined dual-phase output,

only Mode 2 in the OPCFG options can be used. In this mode,

the error amplifiers of both phases are used. The feedback

pins (FB1 and FB2) are tied together, the compensation pins

(COMP1 and COMP2) are tied together, the soft start pins (SS1

and SS2) are tied together, and the enable pins (EN1 and EN2)

are tied together.

In addition, if the power-good feature is used, combine PGOOD1

and PGOOD2 and connect them to VDD through a single

pull-up resistor.

When the ADP2114 is synchronized to an external clock, the

converters always operate in fixed frequency CCM, and they do

not enter into pulse skip mode at light loads. In this case, when

configuring the OPCFG pin, choose forced PWM mode.

Table 7. Current Limit Operation Mode and Configuration

Maximum Output Current

Peak Current Limit

Mode

ROPCFG (Ω) ± 5%

IOUT1 (A)/IOUT2 (A)

ILIMIT1 (A)/ILIMIT2 (A)

Power Savings at Light Load

0 to GND

2/2

3.3/3.3

Pulse skip enabled

4.7 k to GND

2/2

3.3/3.3

Forced PWM

8.2 k to GND

3/1

4.5/1.9

Pulse skip enabled

15 k to GND

3/1

4.5/1.9

Forced PWM

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