ADP2114ACPZ-R7 datasheet(21/40 Pages) AD

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ADP2114

Rev. 0 | Page 21 of 40

THEORY OF OPERATION

UNDERVOLTAGE LOCKOUT (UVLO)

The ADP2114 is a high efficiency, dual, fixed switching frequency,

synchronous step-down, dc-to-dc converter with flex mode

architecture, which is the Analog Devices, Inc., proprietary

version of its peak current mode control architecture. The

device operates over an input voltage range of 2.75 V to 5.5 V.

Each output channel provides an adjustable output down to 0.6 V

and delivers up to 2 A of load current. When both the output

channels are tied together, they operate 180° out of phase to

deliver up to 4 A of load current. The integrated high-side,

P-channel power MOSFET and the low-side, N-channel power

MOSFET yield high efficiency at medium to heavy loads. Pulse

skip mode is available for improved efficiency at light loads. With

its high switching frequency (up to 2 MHz) and its integrated

power switches, the ADP2114 has been optimized to deliver

high performance in a small size for power management solutions.

The UVLO threshold is 2.65 V when VDD is increasing and

2.47 V when VDD is decreasing. The 180 mV hysteresis prevents

the converter from turning off and on repeatedly during a slow

voltage transition on VDD close to the 2.75 V minimum

operational level due to changing load conditions.

ENABLE/DISABLE CONTROL

The EN1 and EN2 pins are used to independently enable or

disable Channel 1 and Channel 2, respectively. Drive ENx high

to turn on the corresponding channel of ADP2114. Drive ENx

low to turn off the corresponding channel of ADP2114, reducing

input current below 1 μA. To force a channel to start automatically

when input power is applied, connect the corresponding ENx

to VDD. When shut down, the ADP2114 channels discharge

the soft start capacitor, causing a new soft start cycle every time

the converters are re-enabled.

The ADP2114 also includes undervoltage lockout (UVLO) with

hysteresis, soft start, and power good, as well as protection

features such as output short-circuit protection and thermal

shutdown. The output voltages, current limits, switching

frequency, pulse skip operation, and soft start time are

externally programmable with tiny resistors and capacitors.

SOFT START

The ADP2114 soft start feature allows the output voltage to ramp

up in a controlled manner, eliminating output voltage overshoot

during startup. Soft start begins after the undervoltage lockout

threshold is exceeded and the enable pin, EN1 (EN2), is pulled

high above 2.0 V. External capacitors to ground are required on

both the SS1 and SS2 pins. Each regulating channel has its own

soft start circuit. When the converter powers up and is enabled,

the internal 6 μA current source charges the external soft start

capacitor, establishing a voltage ramp slope at the SS1 (SS2) pin,

as shown in Figure 66. The soft start time period ends when the

soft start ramp voltage exceeds the internal reference of 0.6 V.

CONTROL ARCHITECTURE

The ADP2114 consists of two step-down, dc-to-dc converters

that deliver regulated output voltages, VOUT1 and VOUT2 (see

Figure 1), by modulating the duty cycle at which the internal

high-side, P-channel power MOSFET and the low-side, N-channel

power MOSFET are switched on and off. In steady-state operation,

the output voltage, VOUT, is sensed on the feedback pin, FB1 (FB2),

and attenuated in proportion to the selected output voltage on

the V1SET (V2SET) pin. An error amplifier integrates the error

between the feedback voltage and the reference voltage (VREF =

0.6 V) to generate an error voltage at the COMP1 (COMP2) pin.

The valley inductor current is sensed by a current-sense amplifier

when the low-side, N-channel MOSFET is on. An internal

oscillator turns off the low-side, N-channel MOSFET and

turns on the high-side, P-channel MOSFET at a fixed switching

frequency. When the high,-side P-channel MOSFET is enabled,

the valley inductor current information is added to an emulated

ramp signal and compared to the error voltage by the PWM

comparator. The output of the PWM comparator modulates the

duty cycle by adjusting the trailing edge of the PWM pulse that

switches the power devices. Slope compensation is programmed

internally into the emulated ramp signal and automatically

selected, depending on the VIN, VOUT, and switching frequency.

This prevents subharmonic oscillations on the inductor current

for greater than 50% duty-cycle operation.

CH3 5.0V

CH2 1.0V

CH1 5.0V

CH4 2.0V

M1.0ms

A CH1

2.4V

ENx

VOUT

SSx

Figure 66. Soft Start

Control logic with the antishoot-through circuit monitor and

adjust the low-side and high-side driver outputs to ensure break-

before-make switching. This monitoring and control prevents

crossconduction between the internal high-side, P-channel

power MOSFET and the low-side, N-channel power MOSFET.

ADP2114ACPZ-R7 数据表(PDF) 21 Page - Analog Devices

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