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ADP5020ACPZ-R7 数据表(PDF) 5 Page - Analog Devices |
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ADP5020ACPZ-R7 数据表(HTML) 5 Page - Analog Devices |
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5 / 28 page ![]() ADP5020 Rev. 0 | Page 5 of 28 SWITCHING SPECIFICATIONS Table 2. Parameter Symbol Conditions Min Typ Max Unit SWITCHING FREQUENCY CH1 fSW1 Sync disabled 2.5 3 3.6 MHz CH2 fSW2 Sync disabled 2.5 3 3.6 MHz SYNC CLOCK DIVIDER RATIO RATIODIV SYNC_9P6 = 1 3 RATIODIV SYNC_19P2 = 1 6 SYNC CHARACTERISTICS Frequency Range fSYNC1 9.6 MHz fSYNC2 19.2 MHz Frequency Duty Cycle fSYNCDUTY 40 50 60 % Signal DC Coupling Level Low Level Input Voltage VIL 0.3 × VDD_IO V High Level Input Voltage VIH 0.7 × VDD_IO V DC Coupling VSYNC 0 VDD_IO V AC Coupling Level VCAC-PP Sine wave, peak-to-peak 0.5 1.0 VDD_IO V AC Coupling Capacitor 10 nF Input Current ISYNC SYNC_9P6 = 1, or SYNC_19P2 = 1 50 μA DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR Table 3. Parameter Symbol Conditions Min Typ Max Unit OUTPUT VOLTAGE Range1 VOUT1 3-bit range 2.5 3.7 V Initial Accuracy TA = 25°C, VDD12, VOUT1 = 3.3 V, ILOAD = 20 mA −1 +1 % Total Accuracy VDD13, ILOAD = 50 mA to 600 mA −5 +4 % VOUT1 REGULATION Load Regulation ILOAD = 20 mA to 600 mA 0.2 % Line Regulation VDDA = 1.8 V, VDD12,3 0.15 % CURRENT Maximum Output Current IBK1MAX VDD13, VOUT1 = 2.5 V to 3.7 V 600 mA Quiescent Current IQBK1 ILOAD = 0 mA 4 6 mA POWER Low-Side Power nMOSFET RDSON1 ID = 400 mA 175 250 mΩ High-Side Power pMOSFET RDSON1 ID = 400 mA 250 400 mΩ SWITCH CURRENT LIMIT ICL1 0.8 1.2 1.6 A MINIMUM ON TIME tMIN1 55 ns MAXIMUM DUTY CYCLE DMAX1 88 95 % SOFT START TIME tSS1 1.4 ms COUT DISCHARGE SWITCH ON RESISTANCE RDIS1 0.7 1 1.3 kΩ 1 See (the BUCK1_VSEL register, Address 0x01) for details. Table 13 2 VDD1 = 3.1 V to 5.5 V, ILOAD is less than 200 mA. For tight regulation, the supply voltage must be 0.6 V higher than the output voltage. 3 VDD1 = 3.7 V to 5.5 V, ILOAD is more than 200 mA. For tight regulation, the supply voltage must be 1.2 V higher than the output voltage. |
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